Fix typos (#6280)

<!---
The core Triton is a small number of people, and we receive many PRs
(thank
you!).  To help us review your code more quickly, **if you are a new
contributor (less than 3 PRs merged) we ask that you complete the
following
tasks and include the filled-out checklist in your PR description.**

Complete the following tasks before sending your PR, and replace `[ ]`
with
`[x]` to indicate you have done them.
-->

# New contributor declaration
- [x] I am not making a trivial change, such as fixing a typo in a
comment.

- [ ] I have written a PR description following these
  [rules](https://cbea.ms/git-commit/#why-not-how).

- [ ] I have run `pre-commit run --from-ref origin/main --to-ref HEAD`.

- Select one of the following.
  - [ ] I have added tests.
    - `/test` for `lit` tests
    - `/unittest` for C++ tests
    - `/python/test` for end-to-end tests
  - [ ] This PR does not need a test because `FILL THIS IN`.

- Select one of the following.
  - [ ] I have not added any `lit` tests.
- [ ] The `lit` tests I have added follow these [best
practices](https://mlir.llvm.org/getting_started/TestingGuide/#filecheck-best-practices),
including the "tests should be minimal" section. (Usually running Python
code
    and using the instructions it generates is not minimal.)

Author: omahs

include/triton/Dialect/TritonGPU/Transforms/PipelineExpander.h

@@ -25,7 +25,7 @@ namespace triton {
 
 /// Options to dictate how loops should be pipelined.
 struct PipeliningOption {
-  /// Lambda returning all the operation in the forOp, with their stage, in the
+  /// Lambda returning all the operations in the forOp, with their stage, in the
   /// order picked for the pipelined loop.
   using GetScheduleFnType = std::function<void(
       scf::ForOp, std::vector<std::pair<Operation *, unsigned>> &)>;
@@ -54,7 +54,7 @@ struct PipeliningOption {
   /// Control whether the transformation checks that the number of iterations is
   /// greater or equal to the number of stages and skip the transformation if
   /// this is not the case. If the loop is dynamic and this is set to true the
-  /// pipeliner will have to predicate operations in the the prologue/epilogue.
+  /// pipeliner will have to predicate operations in the prologue/epilogue.
   bool supportDynamicLoops = false;
 
   // Callback to predicate operations when the prologue or epilogue are not

lib/Dialect/TritonGPU/IR/Dialect.cpp

@@ -1042,7 +1042,7 @@ LinearEncodingAttr::orderPerDim(StringAttr dimName,
 // [Note. Divergence of methods wrt. legacy layouts]
 // For smaller shapes where the CTATile is larger than the output
 // tensor, some methods return different values than the legacy layouts. I think
-// this is benign tho. An example: what is the the vector of `warpsPerCTA` if
+// this is benign tho. An example: what is the vector of `warpsPerCTA` if
 // all the warps hold the same data? I think it should be [1, 1], even if we
 // have 4 warps. But perhaps for this we have to add some masking in some
 // places... We'll see

python/triton/language/core.py

@@ -1574,7 +1574,7 @@ def trans(input: tensor, *dims, _builder=None):
 
     :param input: The input tensor.
     :param dims: The desired ordering of dimensions.  For example,
-        :code:`(2, 1, 0)` reverses the order dims in a a 3D tensor.
+        :code:`(2, 1, 0)` reverses the order dims in a 3D tensor.
 
     :code:`dims` can be passed as a tuple or as individual parameters: ::
 
@@ -1600,7 +1600,7 @@ def permute(input, *dims, _builder=None):
     :param input: The input tensor.
     :type input: Block
     :param dims: The desired ordering of dimensions.  For example,
-        :code:`(2, 1, 0)` reverses the order dims in a a 3D tensor.
+        :code:`(2, 1, 0)` reverses the order dims in a 3D tensor.
 
     :code:`dims` can be passed as a tuple or as individual parameters: ::
 

third_party/amd/backend/include/hip/hip_runtime_api.h

@@ -926,7 +926,7 @@ typedef enum hipMemPoolAttr
  */
  typedef enum hipMemLocationType {
     hipMemLocationTypeInvalid = 0,
-    hipMemLocationTypeDevice = 1    ///< Device location, thus it's HIP device ID
+    hipMemLocationTypeDevice = 1    ///< Device location, thus its HIP device ID
 } hipMemLocationType;
 /**
  * Specifies a memory location.
@@ -4243,7 +4243,7 @@ hipError_t hipGetSymbolSize(size_t* size, const void* symbol);
  * is greater or equal to the version 600, the symbol function will be handle properly as backend
  * compatible function.
  *
- * @param[in] flags  Currently only default flag is suppported.
+ * @param[in] flags  Currently only default flag is supported.
  * @param[out] symbolStatus  Optional enumeration for returned status of searching for symbol driver
  * function based on the input hipVersion.
  *
@@ -5436,7 +5436,7 @@ hipError_t hipDevicePrimaryCtxSetFlags(hipDevice_t dev, unsigned int flags);
  *
  */
 /**
- * @brief Loads code object from file into a module the currrent context.
+ * @brief Loads code object from file into a module in the current context.
  *
  * @param [in] fname  Filename of code object to load
 

third_party/amd/backend/include/hsa/hsa.h

@@ -3594,7 +3594,7 @@ typedef struct hsa_isa_s {
  * @brief Retrieve a reference to an instruction set architecture handle out of
  * a symbolic name.
  *
- * @param[in] name Vendor-specific name associated with a a particular
+ * @param[in] name Vendor-specific name associated with a particular
  * instruction set architecture. @p name must start with the vendor name and a
  * colon (for example, "AMD:"). The rest of the name is vendor-specific. Must be
  * a NUL-terminated string.

third_party/amd/backend/include/hsa/hsa_ext_amd.h

@@ -395,7 +395,7 @@ typedef enum hsa_amd_agent_info_s {
   /**
    * Queries the number of SDMA engines.
    * If HSA_AMD_AGENT_INFO_NUM_SDMA_XGMI_ENG query returns non-zero,
-   * this query returns the the number of SDMA engines optimized for
+   * this query returns the number of SDMA engines optimized for
    * host to device bidirectional traffic.
    * The type of this attribute is uint32_t.
    */

third_party/amd/lib/TritonAMDGPUToLLVM/LoadStoreOpToLLVM.cpp

@@ -121,7 +121,7 @@ struct LoadStoreConversionBase {
                                    ModuleAxisInfoAnalysis &axisAnalysisPass)
       : targetInfo(targetInfo), axisAnalysisPass(axisAnalysisPass) {}
 
-  // Createa a LLVM vector of type `vecTy` containing all zeros
+  // Create a LLVM vector of type `vecTy` containing all zeros
   Value createZeroVector(OpBuilder &builder, Location loc,
                          VectorType vecTy) const {
     mlir::Attribute zeroAttr = builder.getZeroAttr(vecTy.getElementType());