KiCad export drops <copperpour> — emits 0 (zone) blocks despite pcb_copper_pour records in circuit.json

[gsdali]

Summary

tsci export -f kicad_pcb correctly declares the copper layer stack but emits zero (zone) blocks for any pcb_copper_pour records present in circuit.json. Copper pours are silently dropped at the KiCad export step, so opening the resulting .kicad_pcb in KiCad's pcbnew shows pads + traces + silkscreen but no ground plane / pour fills.

Repro

// index.circuit.tsx
export default () => (
  <board width="20mm" height="20mm" layers={2}>
    <chip name="U1" footprint="soic8" pcbX={0} pcbY={0} />
    <copperpour connectsTo="net.GND" layer="bottom" />
  </board>
)

tsci build
jq '[.[] | select(.type=="pcb_copper_pour")] | length' dist/index/circuit.json
# → 1 (or more — pour may auto-fragment, that's fine)

tsci export index.circuit.tsx -f kicad_pcb -o board.kicad_pcb
grep -c '(zone ' board.kicad_pcb
# → 0   ❌ expected ≥ 1

The exported .kicad_pcb has the correct layer stack:

(layers
  (0 "F.Cu" signal)
  (31 "B.Cu" signal)
  ...
)

…but no (zone) blocks at all.

Why this matters

KiCad is currently the only viable visual inspection path for tscircuit pour shapes — the SVG snapshot renderer and the dev viewer don't draw pcb_copper_pour either (see tscircuit/circuit-to-svg — pours render as nothing in the snapshot). With the KiCad exporter dropping zones too, there is no way to visually verify a copper pour outside of opening individual gerbers in gerbv. The gerbers DO contain the pour (G36/G37 region commands in B_Cu.gbr), so the pipeline mostly works; just the KiCad export is missing the translation.

Workaround

Inspect via gerber viewer:

tsci export index.circuit.tsx -f gerbers -o board.gerbers.zip
unzip -d gerbers board.gerbers.zip
gerbv gerbers/B_Cu.gbr   # or F_Cu.gbr

Pour appears correctly here.

Proposed fix

Translate each pcb_copper_pour record's brep_shape.outer_ring.vertices to a KiCad (zone (filled_polygon (pts ...))) block, with (net <id>) resolved from the pour's source_net_id, and (layer <kicad_layer_name>) mapped from the tscircuit layer name (bottom → B.Cu, etc.). Inner rings (cutouts) become (filled_polygon) holes within the zone polygon.

Hit while building an InsightSiP ISP3080-UX daughter board with an antenna keep-out polygon — the pour outline is non-trivial and we needed to verify the keep-out shape visually before fab. KiCad would have been the obvious tool; ended up grepping gerber X2 attributes instead.

[watcharaponthod-code]

Submitted PR #299 which implements AddCopperPoursStage to export pcb_copper_pour records as KiCad (zone) blocks.

Covers rect and polygon shapes. BRep shapes are logged and skipped (pending tessellation support).