diff --git a/lib/utils/autorouting/CapacityMeshAutorouter.ts b/lib/utils/autorouting/CapacityMeshAutorouter.ts index 06ab7f678..4422407c0 100644 --- a/lib/utils/autorouting/CapacityMeshAutorouter.ts +++ b/lib/utils/autorouting/CapacityMeshAutorouter.ts @@ -73,14 +73,14 @@ export class TscircuitAutorouter implements GenericLocalAutorouter { solverName = "AutoroutingPipeline1_OriginalUnravel" } else if (autorouterVersion === "v3") { solverName = "AutoroutingPipelineSolver3_HgPortPointPathing" - } else if (autorouterVersion === "v4") { + } else if (autorouterVersion === "v4" || autorouterVersion === "latest") { solverName = "AutoroutingPipelineSolver4" } else if (useAutoJumperSolver) { solverName = "AssignableAutoroutingPipeline3" } else if (useAssignableSolver) { solverName = "AssignableAutoroutingPipeline2" } else { - solverName = "AutoroutingPipelineSolver" + solverName = "AutoroutingPipelineSolver4" } const SolverClass = SOLVERS[solverName] diff --git a/package.json b/package.json index e81e89b4f..3df71528f 100644 --- a/package.json +++ b/package.json @@ -34,7 +34,7 @@ "@resvg/resvg-js": "^2.6.2", "@tscircuit/alphabet": "0.0.18", "@tscircuit/checks": "0.0.110", - "@tscircuit/capacity-autorouter": "^0.0.353", + "@tscircuit/capacity-autorouter": "^0.0.359", "@tscircuit/circuit-json-util": "^0.0.90", "@tscircuit/common": "^0.0.20", "@tscircuit/copper-pour-solver": "^0.0.20", diff --git a/tests/components/normal-components/__snapshots__/solderjumper-circuit-pcb.snap.svg b/tests/components/normal-components/__snapshots__/solderjumper-circuit-pcb.snap.svg index a87ca40f5..653db9b2d 100644 --- a/tests/components/normal-components/__snapshots__/solderjumper-circuit-pcb.snap.svg +++ b/tests/components/normal-components/__snapshots__/solderjumper-circuit-pcb.snap.svg @@ -1 +1 @@ -R1R2R3J1 \ No newline at end of file +R1R2R3J1 \ No newline at end of file diff --git a/tests/components/primitive-components/__snapshots__/copperpour-multiple-outlines-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/copperpour-multiple-outlines-pcb.snap.svg index 51835db16..20e8cff0c 100644 --- a/tests/components/primitive-components/__snapshots__/copperpour-multiple-outlines-pcb.snap.svg +++ b/tests/components/primitive-components/__snapshots__/copperpour-multiple-outlines-pcb.snap.svg @@ -1 +1 @@ -R1C1 \ No newline at end of file +R1C1 \ No newline at end of file diff --git a/tests/components/primitive-components/__snapshots__/multilayer-resistor-cross2-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/multilayer-resistor-cross2-pcb.snap.svg index 9edb1d33e..1585b81cf 100644 --- a/tests/components/primitive-components/__snapshots__/multilayer-resistor-cross2-pcb.snap.svg +++ b/tests/components/primitive-components/__snapshots__/multilayer-resistor-cross2-pcb.snap.svg @@ -1 +1 @@ -R4R1R2R3 \ No newline at end of file +R4R1R2R3 \ No newline at end of file diff --git a/tests/components/primitive-components/__snapshots__/trace-hint-with-local-autorouter-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/trace-hint-with-local-autorouter-pcb.snap.svg index 0e10be7b8..df7464776 100644 --- a/tests/components/primitive-components/__snapshots__/trace-hint-with-local-autorouter-pcb.snap.svg +++ b/tests/components/primitive-components/__snapshots__/trace-hint-with-local-autorouter-pcb.snap.svg @@ -1 +1 @@ -R1LED1 \ No newline at end of file +R1LED1 \ No newline at end of file diff --git a/tests/components/primitive-components/__snapshots__/trace-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/trace-pcb.snap.svg index 923d5856e..887d0b605 100644 --- a/tests/components/primitive-components/__snapshots__/trace-pcb.snap.svg +++ b/tests/components/primitive-components/__snapshots__/trace-pcb.snap.svg @@ -1 +1 @@ -R1LED1 \ No newline at end of file +R1LED1 \ No newline at end of file diff --git a/tests/components/primitive-components/__snapshots__/via-connect-trace-pcb.snap.svg b/tests/components/primitive-components/__snapshots__/via-connect-trace-pcb.snap.svg index 877511ca6..717b5638e 100644 --- a/tests/components/primitive-components/__snapshots__/via-connect-trace-pcb.snap.svg +++ b/tests/components/primitive-components/__snapshots__/via-connect-trace-pcb.snap.svg @@ -1 +1 @@ -C1TP1TP2 \ No newline at end of file +C1TP1TP2 \ No newline at end of file diff --git a/tests/components/primitive-components/__snapshots__/via-connect-trace-simple-3d.snap.png b/tests/components/primitive-components/__snapshots__/via-connect-trace-simple-3d.snap.png index aa0a96d8a..1bd4ca118 100644 Binary files a/tests/components/primitive-components/__snapshots__/via-connect-trace-simple-3d.snap.png and b/tests/components/primitive-components/__snapshots__/via-connect-trace-simple-3d.snap.png differ diff --git a/tests/drc/__snapshots__/pcb-component-overlap-different-types-pcb.snap.svg b/tests/drc/__snapshots__/pcb-component-overlap-different-types-pcb.snap.svg index bbed9e29b..8b3baba99 100644 --- a/tests/drc/__snapshots__/pcb-component-overlap-different-types-pcb.snap.svg +++ b/tests/drc/__snapshots__/pcb-component-overlap-different-types-pcb.snap.svg @@ -1 +1 @@ -R1C1R2R3pcb_smtpad R1.pin2 overlaps with pcb_smtpad C1.pin1 \ No newline at end of file +R1C1R2R3pcb_smtpad R1.pin2 overlaps with pcb_smtpad C1.pin1 \ No newline at end of file diff --git a/tests/drc/__snapshots__/pcb-component-overlap-pcb.snap.svg b/tests/drc/__snapshots__/pcb-component-overlap-pcb.snap.svg index c0525b269..546353d30 100644 --- a/tests/drc/__snapshots__/pcb-component-overlap-pcb.snap.svg +++ b/tests/drc/__snapshots__/pcb-component-overlap-pcb.snap.svg @@ -1 +1 @@ -R1R2R3R4pcb_smtpad R1.pin2 overlaps with pcb_smtpad R2.pin1pcb_smtpad R1.pin2 overlaps with pcb_smtpad R2.pin2 \ No newline at end of file +R1R2R3R4pcb_smtpad R1.pin2 overlaps with pcb_smtpad R2.pin1pcb_smtpad R1.pin2 overlaps with pcb_smtpad R2.pin2 \ No newline at end of file diff --git a/tests/drc/__snapshots__/pcb-plated-hole-overlap-pcb.snap.svg b/tests/drc/__snapshots__/pcb-plated-hole-overlap-pcb.snap.svg index 98e1b65b5..c18a2d01c 100644 --- a/tests/drc/__snapshots__/pcb-plated-hole-overlap-pcb.snap.svg +++ b/tests/drc/__snapshots__/pcb-plated-hole-overlap-pcb.snap.svg @@ -1 +1 @@ -U1U2{pin1}{pin2}{pin3}{pin4}{pin5}{pin6}{pin7}{pin8}{pin1}{pin2}{pin3}{pin4}{pin5}{pin6}{pin7}{pin8}pcb_plated_hole U1.pin1 overlaps with pcb_plated_hole U2.pin1pcb_plated_hole U1.pin1 overlaps with pcb_plated_hole U2.pin2pcb_plated_hole U1.pin2 overlaps with pcb_plated_hole U2.pin2pcb_plated_hole U1.pin2 overlaps with pcb_plated_hole U2.pin3pcb_plated_hole U1.pin3 overlaps with pcb_plated_hole U2.pin3pcb_plated_hole U1.pin3 overlaps with pcb_plated_hole U2.pin4pcb_plated_hole U1.pin4 overlaps with pcb_plated_hole U2.pin4pcb_plated_hole U1.pin5 overlaps with pcb_plated_hole U2.pin5pcb_plated_hole U1.pin6 overlaps with pcb_plated_hole U2.pin5pcb_plated_hole U1.pin6 overlaps with pcb_plated_hole U2.pin6pcb_plated_hole U1.pin7 overlaps with pcb_plated_hole U2.pin6pcb_plated_hole U1.pin7 overlaps with pcb_plated_hole U2.pin7pcb_plated_hole U1.pin8 overlaps with pcb_plated_hole U2.pin7pcb_plated_hole U1.pin8 overlaps with pcb_plated_hole U2.pin8Courtyard of U1 overlaps with courtyard of U2 \ No newline at end of file +U1U2{pin1}{pin2}{pin3}{pin4}{pin5}{pin6}{pin7}{pin8}{pin1}{pin2}{pin3}{pin4}{pin5}{pin6}{pin7}{pin8}PCB trace trace[.U2 > port.8, .U1 > port.1] overlaps with pcb_plated_hole "pcb_plated_hole[#pcb_plated_hole_8]" (accidental contact)pcb_plated_hole U1.pin1 overlaps with pcb_plated_hole U2.pin1pcb_plated_hole U1.pin1 overlaps with pcb_plated_hole U2.pin2pcb_plated_hole U1.pin2 overlaps with pcb_plated_hole U2.pin2pcb_plated_hole U1.pin2 overlaps with pcb_plated_hole U2.pin3pcb_plated_hole U1.pin3 overlaps with pcb_plated_hole U2.pin3pcb_plated_hole U1.pin3 overlaps with pcb_plated_hole U2.pin4pcb_plated_hole U1.pin4 overlaps with pcb_plated_hole U2.pin4pcb_plated_hole U1.pin5 overlaps with pcb_plated_hole U2.pin5pcb_plated_hole U1.pin6 overlaps with pcb_plated_hole U2.pin5pcb_plated_hole U1.pin6 overlaps with pcb_plated_hole U2.pin6pcb_plated_hole U1.pin7 overlaps with pcb_plated_hole U2.pin6pcb_plated_hole U1.pin7 overlaps with pcb_plated_hole U2.pin7pcb_plated_hole U1.pin8 overlaps with pcb_plated_hole U2.pin7pcb_plated_hole U1.pin8 overlaps with pcb_plated_hole U2.pin8Courtyard of U1 overlaps with courtyard of U2 \ No newline at end of file diff --git a/tests/examples/__snapshots__/example29-copper-pour.test.tsx-cutouts-and-vias-pcb.snap.svg b/tests/examples/__snapshots__/example29-copper-pour.test.tsx-cutouts-and-vias-pcb.snap.svg index edef32997..06e4a07ad 100644 --- a/tests/examples/__snapshots__/example29-copper-pour.test.tsx-cutouts-and-vias-pcb.snap.svg +++ b/tests/examples/__snapshots__/example29-copper-pour.test.tsx-cutouts-and-vias-pcb.snap.svg @@ -1 +1 @@ -C1R1 \ No newline at end of file +C1R1 \ No newline at end of file diff --git a/tests/examples/__snapshots__/example29-copper-pour.test.tsx-polygon-board-pcb.snap.svg b/tests/examples/__snapshots__/example29-copper-pour.test.tsx-polygon-board-pcb.snap.svg index 6330031ea..0f3c1a39a 100644 --- a/tests/examples/__snapshots__/example29-copper-pour.test.tsx-polygon-board-pcb.snap.svg +++ b/tests/examples/__snapshots__/example29-copper-pour.test.tsx-polygon-board-pcb.snap.svg @@ -1 +1 @@ -U1R1C1 \ No newline at end of file +U1R1C1 \ No newline at end of file diff --git a/tests/examples/__snapshots__/example29-copper-pour.test.tsx-smaller-trace-margin-pcb.snap.svg b/tests/examples/__snapshots__/example29-copper-pour.test.tsx-smaller-trace-margin-pcb.snap.svg index 874f7ad99..4573e7c81 100644 --- a/tests/examples/__snapshots__/example29-copper-pour.test.tsx-smaller-trace-margin-pcb.snap.svg +++ b/tests/examples/__snapshots__/example29-copper-pour.test.tsx-smaller-trace-margin-pcb.snap.svg @@ -1 +1 @@ -U1R1C1 \ No newline at end of file +U1R1C1 \ No newline at end of file diff --git a/tests/examples/__snapshots__/example29-copper-pour.test.tsxbigger-trace-margin-pcb.snap.svg b/tests/examples/__snapshots__/example29-copper-pour.test.tsxbigger-trace-margin-pcb.snap.svg index e932ecc5a..89c7343d8 100644 --- a/tests/examples/__snapshots__/example29-copper-pour.test.tsxbigger-trace-margin-pcb.snap.svg +++ b/tests/examples/__snapshots__/example29-copper-pour.test.tsxbigger-trace-margin-pcb.snap.svg @@ -1 +1 @@ -U1R1C1 \ No newline at end of file +U1R1C1 \ No newline at end of file diff --git a/tests/examples/__snapshots__/example3-3x3-keyboard-pcb.snap.svg b/tests/examples/__snapshots__/example3-3x3-keyboard-pcb.snap.svg index 7c3678cad..d5676c4e7 100644 --- a/tests/examples/__snapshots__/example3-3x3-keyboard-pcb.snap.svg +++ b/tests/examples/__snapshots__/example3-3x3-keyboard-pcb.snap.svg @@ -1 +1 @@ -D1D2D3D4D5D6D7D8D9U1{pin1}{pin2}{pin3}{pin4}{pin5}{pin6}{pin7}{pin8}{pin9}{pin10}{pin11}{pin12}{pin13}{pin14}{pin15}{pin16}{pin17}{pin18}{pin19}{pin20}{pin21}{pin22}{pin23}{pin24} \ No newline at end of file +D1D2D3D4D5D6D7D8D9U1{pin1}{pin2}{pin3}{pin4}{pin5}{pin6}{pin7}{pin8}{pin9}{pin10}{pin11}{pin12}{pin13}{pin14}{pin15}{pin16}{pin17}{pin18}{pin19}{pin20}{pin21}{pin22}{pin23}{pin24} \ No newline at end of file diff --git a/tests/examples/__snapshots__/example33-3d-pinheader-jumper-simple-3d.snap.png b/tests/examples/__snapshots__/example33-3d-pinheader-jumper-simple-3d.snap.png index 7719f20bb..14e4343c9 100644 Binary files a/tests/examples/__snapshots__/example33-3d-pinheader-jumper-simple-3d.snap.png and b/tests/examples/__snapshots__/example33-3d-pinheader-jumper-simple-3d.snap.png differ diff --git a/tests/features/__snapshots__/capacity-mesh-autorouting1-pcb.snap.svg b/tests/features/__snapshots__/capacity-mesh-autorouting1-pcb.snap.svg index af8f9f33f..4f5cd1482 100644 --- a/tests/features/__snapshots__/capacity-mesh-autorouting1-pcb.snap.svg +++ b/tests/features/__snapshots__/capacity-mesh-autorouting1-pcb.snap.svg @@ -1 +1 @@ -R1R2_obstacleLED1 \ No newline at end of file +R1R2_obstacleLED1 \ No newline at end of file diff --git a/tests/features/capacity-mesh-autorouting1.test.tsx b/tests/features/capacity-mesh-autorouting1.test.tsx index 2c834e38d..af7987d16 100644 --- a/tests/features/capacity-mesh-autorouting1.test.tsx +++ b/tests/features/capacity-mesh-autorouting1.test.tsx @@ -3,6 +3,11 @@ import { getTestFixture } from "../fixtures/get-test-fixture" test("board with local group autorouter (capacity mesh)", async () => { const { circuit } = getTestFixture() + let solverStartedName: string | undefined + + circuit.on("solver:started", (event) => { + solverStartedName = event.solverName + }) // Create a circuit with two components that need to be connected by a trace // The capacity mesh autorouter will be used to find the optimal route @@ -41,6 +46,7 @@ test("board with local group autorouter (capacity mesh)", async () => { // Verify that we have PCB traces in the output const traces = circuit.selectAll("trace") expect(traces.length).toBeGreaterThan(0) + expect(solverStartedName).toBe("AutoroutingPipelineSolver4") // Match against a PCB snapshot to verify routing expect(circuit).toMatchPcbSnapshot(import.meta.path) diff --git a/tests/features/group-ports/__snapshots__/group-ports01-pcb.snap.svg b/tests/features/group-ports/__snapshots__/group-ports01-pcb.snap.svg index 4bf4da361..945fde3a2 100644 --- a/tests/features/group-ports/__snapshots__/group-ports01-pcb.snap.svg +++ b/tests/features/group-ports/__snapshots__/group-ports01-pcb.snap.svg @@ -1 +1 @@ -R_INSIDE_GROUPR_OUTSIDE \ No newline at end of file +R_INSIDE_GROUPR_OUTSIDE \ No newline at end of file diff --git a/tests/features/subcircuit-circuit-json/__snapshots__/subcircuit-circuit-json02-pcb.snap.svg b/tests/features/subcircuit-circuit-json/__snapshots__/subcircuit-circuit-json02-pcb.snap.svg index 93aa8588b..e1b9a4018 100644 --- a/tests/features/subcircuit-circuit-json/__snapshots__/subcircuit-circuit-json02-pcb.snap.svg +++ b/tests/features/subcircuit-circuit-json/__snapshots__/subcircuit-circuit-json02-pcb.snap.svg @@ -1 +1 @@ -U1R1R2 \ No newline at end of file +U1R1R2 \ No newline at end of file diff --git a/tests/footprint/__snapshots__/footprint-library-map2-pcb.snap.svg b/tests/footprint/__snapshots__/footprint-library-map2-pcb.snap.svg index a948313b5..78e1dbf40 100644 --- a/tests/footprint/__snapshots__/footprint-library-map2-pcb.snap.svg +++ b/tests/footprint/__snapshots__/footprint-library-map2-pcb.snap.svg @@ -1 +1 @@ -R2R1R1R1 \ No newline at end of file +R2R1R1R1 \ No newline at end of file diff --git a/tests/groups/__snapshots__/group-subcircuit-no-duplicate-trace-pcb.snap.svg b/tests/groups/__snapshots__/group-subcircuit-no-duplicate-trace-pcb.snap.svg index aa5315c7b..5ee64b3a9 100644 --- a/tests/groups/__snapshots__/group-subcircuit-no-duplicate-trace-pcb.snap.svg +++ b/tests/groups/__snapshots__/group-subcircuit-no-duplicate-trace-pcb.snap.svg @@ -1 +1 @@ -R3R4C1C2 \ No newline at end of file +R3R4C1C2 \ No newline at end of file diff --git a/tests/pcb-packing/repros/__snapshots__/repro1-packing-imported-board-pcb.snap.svg b/tests/pcb-packing/repros/__snapshots__/repro1-packing-imported-board-pcb.snap.svg index d75f377fd..78a9a5d64 100644 --- a/tests/pcb-packing/repros/__snapshots__/repro1-packing-imported-board-pcb.snap.svg +++ b/tests/pcb-packing/repros/__snapshots__/repro1-packing-imported-board-pcb.snap.svg @@ -1 +1 @@ -pin1pin2pin3pin4pin5J1_greenpillR1_greenpillC1_greenpillC2R2LED_PWR \ No newline at end of file +pin1pin2pin3pin4pin5J1_greenpillR1_greenpillC1_greenpillC2R2LED_PWR \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro11-hover-trace-with-new-autorouter-pcb.snap.svg b/tests/repros/__snapshots__/repro11-hover-trace-with-new-autorouter-pcb.snap.svg index f41de9e6b..c212069e6 100644 --- a/tests/repros/__snapshots__/repro11-hover-trace-with-new-autorouter-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro11-hover-trace-with-new-autorouter-pcb.snap.svg @@ -1 +1 @@ -R1LED1 \ No newline at end of file +R1LED1 \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro23-trace-overlap-pcb.snap.svg b/tests/repros/__snapshots__/repro23-trace-overlap-pcb.snap.svg index 8ad29110b..02b10d421 100644 --- a/tests/repros/__snapshots__/repro23-trace-overlap-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro23-trace-overlap-pcb.snap.svg @@ -1 +1 @@ -GNDN_RESETpin3SWOSWDCLKSWDIOVCCGNDGNDpin10J2SCLSDAGNDGNDSCKMISOMOSIA10A9A8JP12 \ No newline at end of file +GNDN_RESETpin3SWOSWDCLKSWDIOVCCGNDGNDpin10J2SCLSDAGNDGNDSCKMISOMOSIA10A9A8JP12 \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro33-minimal-tilt-pcb.snap.svg b/tests/repros/__snapshots__/repro33-minimal-tilt-pcb.snap.svg index b9e736d99..7eae50ff8 100644 --- a/tests/repros/__snapshots__/repro33-minimal-tilt-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro33-minimal-tilt-pcb.snap.svg @@ -1 +1 @@ -U1R1 \ No newline at end of file +U1R1 \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro44-e2e-pack-and-schematic-pcb.snap.svg b/tests/repros/__snapshots__/repro44-e2e-pack-and-schematic-pcb.snap.svg index 93d5cdaf4..84bcc5612 100644 --- a/tests/repros/__snapshots__/repro44-e2e-pack-and-schematic-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro44-e2e-pack-and-schematic-pcb.snap.svg @@ -1 +1 @@ -U1R1R2C1C2R3 \ No newline at end of file +U1R1R2C1C2R3 \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro48-555-timer-pcb.snap.svg b/tests/repros/__snapshots__/repro48-555-timer-pcb.snap.svg index cf46c8251..9216b51e0 100644 --- a/tests/repros/__snapshots__/repro48-555-timer-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro48-555-timer-pcb.snap.svg @@ -1 +1 @@ -U1R1R2C1C2VCCOUTGNDJ1 \ No newline at end of file +U1R1R2C1C2VCCOUTGNDJ1 \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro60-arduino-shield-components-outside-board-pcb.snap.svg b/tests/repros/__snapshots__/repro60-arduino-shield-components-outside-board-pcb.snap.svg index a2ed9e4df..587a364db 100644 --- a/tests/repros/__snapshots__/repro60-arduino-shield-components-outside-board-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro60-arduino-shield-components-outside-board-pcb.snap.svg @@ -1 +1 @@ -A0A1A2A3A4A5VINGND1GND0V5V3_3RESIOREFNCD7D6D5D4D3D2TXRXD8D9D10D11D12D13GND2AREFSDASCLR1LED1 \ No newline at end of file +A0A1A2A3A4A5VINGND1GND0V5V3_3RESIOREFNCD7D6D5D4D3D2TXRXD8D9D10D11D12D13GND2AREFSDASCLR1LED1 \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro62-xiao-board-rp2040-pcb-packing-pcb.snap.svg b/tests/repros/__snapshots__/repro62-xiao-board-rp2040-pcb-packing-pcb.snap.svg index 50e427901..fd46d7532 100644 --- a/tests/repros/__snapshots__/repro62-xiao-board-rp2040-pcb-packing-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro62-xiao-board-rp2040-pcb-packing-pcb.snap.svg @@ -1 +1 @@ -C5C2C3C7C10C15C18C21 \ No newline at end of file +C5C2C3C7C10C15C18C21 \ No newline at end of file diff --git a/tests/repros/__snapshots__/repro76-false-positive-accidental-contact-drc-pcb.snap.svg b/tests/repros/__snapshots__/repro76-false-positive-accidental-contact-drc-pcb.snap.svg index 377713e64..3d59910f5 100644 --- a/tests/repros/__snapshots__/repro76-false-positive-accidental-contact-drc-pcb.snap.svg +++ b/tests/repros/__snapshots__/repro76-false-positive-accidental-contact-drc-pcb.snap.svg @@ -1 +1 @@ -pin1pin2pin3J1_greenpill \ No newline at end of file +pin1pin2pin3J1_greenpillPCB trace trace[.J1_greenpill > port.3, .U1 > port.pin9] overlaps with pcb_smtpad "pcb_port[.U1 > .pin10]" (gap: 0.067mm) \ No newline at end of file diff --git a/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-panel-pcb.snap.svg b/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-panel-pcb.snap.svg index 2c67425b2..bef857c10 100644 --- a/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-panel-pcb.snap.svg +++ b/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-panel-pcb.snap.svg @@ -1 +1 @@ -LEDR1LEDR1LEDR1R1C1 \ No newline at end of file +LEDR1LEDR1LEDR1R1C1 \ No newline at end of file diff --git a/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-pcb.snap.svg b/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-pcb.snap.svg index ab0a64014..dcd91097c 100644 --- a/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-pcb.snap.svg +++ b/tests/repros/repro10-usb-c-flashlight/__snapshots__/repro10-usbc-flashlight-pcb.snap.svg @@ -1 +1 @@ -LEDR1 \ No newline at end of file +LEDR1 \ No newline at end of file diff --git a/tests/repros/repro76-false-positive-accidental-contact-drc.test.tsx b/tests/repros/repro76-false-positive-accidental-contact-drc.test.tsx index 02d8682a0..e8ab0e6d2 100644 --- a/tests/repros/repro76-false-positive-accidental-contact-drc.test.tsx +++ b/tests/repros/repro76-false-positive-accidental-contact-drc.test.tsx @@ -5,7 +5,13 @@ test("false positive accidental contact DRC (simplified) - fixed", async () => { const { circuit } = getTestFixture() circuit.add( - +