Merge branch 'adc_support'

Author: edy555

halconf.h

@@ -41,7 +41,7 @@
  * @brief   Enables the ADC subsystem.
  */
 #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
-#define HAL_USE_ADC                 FALSE
+#define HAL_USE_ADC                 TRUE
 #endif
 
 /**

main.c

@@ -374,6 +374,27 @@ measure_power_dbm(void)
   measured_power_dbm = dbm;
 }
 
+uint16_t adc_single_read(ADC_TypeDef *adc, uint32_t chsel)
+{
+  /* ADC setup */
+  adc->ISR    = adc->ISR;
+  adc->IER    = 0;
+  adc->SMPR1  = ADC_SMPR1_SMP0_2; // 19.5 cycle
+  adc->CFGR   = 0; // 12bit
+  adc->SQR1   = chsel << 6;
+
+  /* ADC conversion start.*/
+  adc->CR |= ADC_CR_ADSTART;
+  while (adc->CR & ADC_CR_ADSTART)
+    ;
+
+  return adc->DR;
+}
+
+#define ADC1_CHANNEL_TEMP 16
+#define ADC1_CHANNEL_BAT  17
+#define ADC1_CHANNEL_VREF 18
+
 static void cmd_stat(BaseSequentialStream *chp, int argc, char *argv[])
 {
   (void)argc;
@@ -394,6 +415,10 @@ static void cmd_stat(BaseSequentialStream *chp, int argc, char *argv[])
   chprintf(chp, "fm stereo: %d %d\r\n", stereo_separate_state.sdi, stereo_separate_state.sdq);
   chprintf(chp, "  corr: %d %d %d\r\n", stereo_separate_state.corr, stereo_separate_state.corr_ave, stereo_separate_state.corr_std);
   chprintf(chp, "  int: %d\r\n", stereo_separate_state.integrator);
+
+  chprintf(chp, "temp: %d\r\n", adc_single_read(ADC1, ADC1_CHANNEL_TEMP));
+  chprintf(chp, "bat: %d\r\n", adc_single_read(ADC1, ADC1_CHANNEL_BAT));
+  chprintf(chp, "vref: %d\r\n", adc_single_read(ADC1, ADC1_CHANNEL_VREF));
 
 #if 0
   p = &tx_buffer[0];
@@ -831,6 +856,15 @@ int __attribute__((noreturn)) main(void)
   dac1cfg1.init = config.dac_value;
   dacStart(&DACD1, &dac1cfg1);
 
+  /*
+   * Activates the ADC1 driver and the temperature sensor.
+   */
+  adcStart(&ADCD1, NULL);
+  adcSTM32EnableTS(&ADCD1);
+  adcSTM32EnableVBAT(&ADCD1);
+  adcSTM32EnableVREF(&ADCD1);
+
+  
   i2cStart(&I2CD1, &i2ccfg);
   /*
    * Initializes a serial-over-USB CDC driver.

mcuconf.h

@@ -53,7 +53,7 @@
 #define STM32_PPRE1                         STM32_PPRE1_DIV2
 #define STM32_PPRE2                         STM32_PPRE2_DIV1
 #define STM32_MCOSEL                        STM32_MCOSEL_PLLDIV2
-#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1
+#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV64
 #define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1
 #define STM32_USART1SW                      STM32_USART1SW_PCLK
 #define STM32_USART2SW                      STM32_USART2SW_PCLK
@@ -71,15 +71,19 @@
 /*
  * ADC driver system settings.
  */
-#define STM32_ADC_USE_ADC1                  FALSE
+#define STM32_ADC_USE_ADC1                  TRUE
 #define STM32_ADC_USE_ADC3                  FALSE
+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
 #define STM32_ADC_ADC12_DMA_PRIORITY        2
 #define STM32_ADC_ADC34_DMA_PRIORITY        2
 #define STM32_ADC_ADC12_IRQ_PRIORITY        5
 #define STM32_ADC_ADC34_IRQ_PRIORITY        5
 #define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5
 #define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5
-#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV4
 #define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
 #define STM32_ADC_DUAL_MODE                 FALSE