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2403 lines (2403 loc) · 126 KB
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InstructionSet XCoreVSimd extends RISCVBase {
instructions {
// SOURCE FILE: instr_srcs/XCoreVSIMD_ALU.txt
CV_ADD_H {
encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.add.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] + X[rs2][15: 0])[15:0];
X[rd][31:16] = (X[rs1][31:16] + X[rs2][31:16])[15:0];
}
}
}
CV_ADD_SC_H {
encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.add.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] + X[rs2][15:0])[15:0];
X[rd][31:16] = (X[rs1][31:16] + X[rs2][15:0])[15:0];
}
}
}
CV_ADD_SCI_H {
encoding: 5'b00000 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.add.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] + ((unsigned<16>)((signed)Imm6)))[15:0];
X[rd][31:16] = (X[rs1][31:16] + ((unsigned<16>)((signed)Imm6)))[15:0];
}
}
}
CV_ADD_B {
encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.add.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] + X[rs2][ 7: 0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] + X[rs2][15: 8])[7:0];
X[rd][23:16] = (X[rs1][23:16] + X[rs2][23:16])[7:0];
X[rd][31:24] = (X[rs1][31:24] + X[rs2][31:24])[7:0];
}
}
}
CV_ADD_SC_B {
encoding: 5'b00000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.add.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] + X[rs2][7:0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] + X[rs2][7:0])[7:0];
X[rd][23:16] = (X[rs1][23:16] + X[rs2][7:0])[7:0];
X[rd][31:24] = (X[rs1][31:24] + X[rs2][7:0])[7:0];
}
}
}
CV_ADD_SCI_B {
encoding: 5'b00000 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.add.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] + ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][15: 8] = (X[rs1][15: 8] + ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][23:16] = (X[rs1][23:16] + ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][31:24] = (X[rs1][31:24] + ((unsigned<8>)((signed)Imm6)))[7:0];
}
}
}
CV_SUB_H {
encoding: 5'b00001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sub.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] - X[rs2][15: 0])[15:0];
X[rd][31:16] = (X[rs1][31:16] - X[rs2][31:16])[15:0];
}
}
}
CV_SUB_SC_H {
encoding: 5'b00001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sub.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] - X[rs2][15:0])[15:0];
X[rd][31:16] = (X[rs1][31:16] - X[rs2][15:0])[15:0];
}
}
}
CV_SUB_SCI_H {
encoding: 5'b00001 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sub.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] - ((unsigned<16>)((signed)Imm6)))[15:0];
X[rd][31:16] = (X[rs1][31:16] - ((unsigned<16>)((signed)Imm6)))[15:0];
}
}
}
CV_SUB_B {
encoding: 5'b00001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sub.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] - X[rs2][ 7: 0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] - X[rs2][15: 8])[7:0];
X[rd][23:16] = (X[rs1][23:16] - X[rs2][23:16])[7:0];
X[rd][31:24] = (X[rs1][31:24] - X[rs2][31:24])[7:0];
}
}
}
CV_SUB_SC_B {
encoding: 5'b00001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sub.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] - X[rs2][7:0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] - X[rs2][7:0])[7:0];
X[rd][23:16] = (X[rs1][23:16] - X[rs2][7:0])[7:0];
X[rd][31:24] = (X[rs1][31:24] - X[rs2][7:0])[7:0];
}
}
}
CV_SUB_SCI_B {
encoding: 5'b00001 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sub.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] - ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][15: 8] = (X[rs1][15: 8] - ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][23:16] = (X[rs1][23:16] - ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][31:24] = (X[rs1][31:24] - ((unsigned<8>)((signed)Imm6)))[7:0];
}
}
}
CV_AVG_H {
encoding: 5'b00010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avg.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)(X[rs1][15: 0] + X[rs2][15: 0]) >> 1)[15:0];
X[rd][31:16] = ((signed)(X[rs1][31:16] + X[rs2][31:16]) >> 1)[15:0];
}
}
}
CV_AVG_SC_H {
encoding: 5'b00010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avg.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)(X[rs1][15: 0] + X[rs2][15:0]) >> 1)[15:0];
X[rd][31:16] = ((signed)(X[rs1][31:16] + X[rs2][15:0]) >> 1)[15:0];
}
}
}
CV_AVG_SCI_H {
encoding: 5'b00010 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avg.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)(X[rs1][15: 0] + ((unsigned<16>)((signed)Imm6))) >> 1)[15:0];
X[rd][31:16] = ((signed)(X[rs1][31:16] + ((unsigned<16>)((signed)Imm6))) >> 1)[15:0];
}
}
}
CV_AVG_B {
encoding: 5'b00010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avg.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)(X[rs1][ 7: 0] + X[rs2][ 7: 0]) >> 1)[7:0];
X[rd][15: 8] = ((signed)(X[rs1][15: 8] + X[rs2][15: 8]) >> 1)[7:0];
X[rd][23:16] = ((signed)(X[rs1][23:16] + X[rs2][23:16]) >> 1)[7:0];
X[rd][31:24] = ((signed)(X[rs1][31:24] + X[rs2][31:24]) >> 1)[7:0];
}
}
}
CV_AVG_SC_B {
encoding: 5'b00010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avg.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)(X[rs1][ 7: 0] + X[rs2][7:0]) >> 1)[7:0];
X[rd][15: 8] = ((signed)(X[rs1][15: 8] + X[rs2][7:0]) >> 1)[7:0];
X[rd][23:16] = ((signed)(X[rs1][23:16] + X[rs2][7:0]) >> 1)[7:0];
X[rd][31:24] = ((signed)(X[rs1][31:24] + X[rs2][7:0]) >> 1)[7:0];
}
}
}
CV_AVG_SCI_B {
encoding: 5'b00010 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avg.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)(X[rs1][ 7: 0] + ((unsigned<8>)((signed)Imm6))) >> 1)[7:0];
X[rd][15: 8] = ((signed)(X[rs1][15: 8] + ((unsigned<8>)((signed)Imm6))) >> 1)[7:0];
X[rd][23:16] = ((signed)(X[rs1][23:16] + ((unsigned<8>)((signed)Imm6))) >> 1)[7:0];
X[rd][31:24] = ((signed)(X[rs1][31:24] + ((unsigned<8>)((signed)Imm6))) >> 1)[7:0];
}
}
}
CV_AVGU_H {
encoding: 5'b00011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avgu.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)(X[rs1][15: 0] + X[rs2][15: 0]) >> 1)[15:0];
X[rd][31:16] = ((unsigned)(X[rs1][31:16] + X[rs2][31:16]) >> 1)[15:0];
}
}
}
CV_AVGU_SC_H {
encoding: 5'b00011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avgu.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)(X[rs1][15: 0] + X[rs2][15:0]) >> 1)[15:0];
X[rd][31:16] = ((unsigned)(X[rs1][31:16] + X[rs2][15:0]) >> 1)[15:0];
}
}
}
CV_AVGU_SCI_H {
encoding: 5'b00011 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avgu.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)(X[rs1][15: 0] + ((unsigned<16>)Imm6)) >> 1)[15:0];
X[rd][31:16] = ((unsigned)(X[rs1][31:16] + ((unsigned<16>)Imm6)) >> 1)[15:0];
}
}
}
CV_AVGU_B {
encoding: 5'b00011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avgu.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)(X[rs1][ 7: 0] + X[rs2][ 7: 0]) >> 1)[7:0];
X[rd][15: 8] = ((unsigned)(X[rs1][15: 8] + X[rs2][15: 8]) >> 1)[7:0];
X[rd][23:16] = ((unsigned)(X[rs1][23:16] + X[rs2][23:16]) >> 1)[7:0];
X[rd][31:24] = ((unsigned)(X[rs1][31:24] + X[rs2][31:24]) >> 1)[7:0];
}
}
}
CV_AVGU_SC_B {
encoding: 5'b00011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avgu.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)(X[rs1][ 7: 0] + X[rs2][7:0]) >> 1)[7:0];
X[rd][15: 8] = ((unsigned)(X[rs1][15: 8] + X[rs2][7:0]) >> 1)[7:0];
X[rd][23:16] = ((unsigned)(X[rs1][23:16] + X[rs2][7:0]) >> 1)[7:0];
X[rd][31:24] = ((unsigned)(X[rs1][31:24] + X[rs2][7:0]) >> 1)[7:0];
}
}
}
CV_AVGU_SCI_B {
encoding: 5'b00011 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.avgu.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)(X[rs1][ 7: 0] + ((unsigned<8>)Imm6)) >> 1)[7:0];
X[rd][15: 8] = ((unsigned)(X[rs1][15: 8] + ((unsigned<8>)Imm6)) >> 1)[7:0];
X[rd][23:16] = ((unsigned)(X[rs1][23:16] + ((unsigned<8>)Imm6)) >> 1)[7:0];
X[rd][31:24] = ((unsigned)(X[rs1][31:24] + ((unsigned<8>)Imm6)) >> 1)[7:0];
}
}
}
CV_MIN_H {
encoding: 5'b00100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.min.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)X[rs1][15: 0] < (signed)X[rs2][15: 0]) ? X[rs1][15: 0] : X[rs2][15: 0];
X[rd][31:16] = ((signed)X[rs1][31:16] < (signed)X[rs2][31:16]) ? X[rs1][31:16] : X[rs2][31:16];
}
}
}
CV_MIN_SC_H {
encoding: 5'b00100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.min.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)X[rs1][15: 0] < (signed)X[rs2][15:0]) ? X[rs1][15: 0] : X[rs2][15:0];
X[rd][31:16] = ((signed)X[rs1][31:16] < (signed)X[rs2][15:0]) ? X[rs1][31:16] : X[rs2][15:0];
}
}
}
CV_MIN_SCI_H {
encoding: 5'b00100 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.min.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)X[rs1][15: 0] < (signed)((unsigned<16>)((signed)Imm6))) ? X[rs1][15: 0] : ((unsigned<16>)((signed)Imm6));
X[rd][31:16] = ((signed)X[rs1][31:16] < (signed)((unsigned<16>)((signed)Imm6))) ? X[rs1][31:16] : ((unsigned<16>)((signed)Imm6));
}
}
}
CV_MIN_B {
encoding: 5'b00100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.min.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)X[rs1][ 7: 0] < (signed)X[rs2][ 7: 0]) ? X[rs1][ 7: 0] : X[rs2][ 7: 0];
X[rd][15: 8] = ((signed)X[rs1][15: 8] < (signed)X[rs2][15: 8]) ? X[rs1][15: 8] : X[rs2][15: 8];
X[rd][23:16] = ((signed)X[rs1][23:16] < (signed)X[rs2][23:16]) ? X[rs1][23:16] : X[rs2][23:16];
X[rd][31:24] = ((signed)X[rs1][31:24] < (signed)X[rs2][31:24]) ? X[rs1][31:24] : X[rs2][31:24];
}
}
}
CV_MIN_SC_B {
encoding: 5'b00100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.min.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)X[rs1][ 7: 0] < (signed)X[rs2][7:0]) ? X[rs1][ 7: 0] : X[rs2][7:0];
X[rd][15: 8] = ((signed)X[rs1][15: 8] < (signed)X[rs2][7:0]) ? X[rs1][15: 8] : X[rs2][7:0];
X[rd][23:16] = ((signed)X[rs1][23:16] < (signed)X[rs2][7:0]) ? X[rs1][23:16] : X[rs2][7:0];
X[rd][31:24] = ((signed)X[rs1][31:24] < (signed)X[rs2][7:0]) ? X[rs1][31:24] : X[rs2][7:0];
}
}
}
CV_MIN_SCI_B {
encoding: 5'b00100 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.min.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)X[rs1][ 7: 0] < (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][ 7: 0] : ((unsigned<8>)((signed)Imm6));
X[rd][15: 8] = ((signed)X[rs1][15: 8] < (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][15: 8] : ((unsigned<8>)((signed)Imm6));
X[rd][23:16] = ((signed)X[rs1][23:16] < (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][23:16] : ((unsigned<8>)((signed)Imm6));
X[rd][31:24] = ((signed)X[rs1][31:24] < (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][31:24] : ((unsigned<8>)((signed)Imm6));
}
}
}
CV_MINU_H {
encoding: 5'b00101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.minu.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)X[rs1][15: 0] < (unsigned)X[rs2][15: 0]) ? X[rs1][15: 0] : X[rs2][15: 0];
X[rd][31:16] = ((unsigned)X[rs1][31:16] < (unsigned)X[rs2][31:16]) ? X[rs1][31:16] : X[rs2][31:16];
}
}
}
CV_MINU_SC_H {
encoding: 5'b00101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.minu.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)X[rs1][15: 0] < (unsigned)X[rs2][15:0]) ? X[rs1][15: 0] : X[rs2][15:0];
X[rd][31:16] = ((unsigned)X[rs1][31:16] < (unsigned)X[rs2][15:0]) ? X[rs1][31:16] : X[rs2][15:0];
}
}
}
CV_MINU_SCI_H {
encoding: 5'b00101 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.minu.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)X[rs1][15: 0] < (unsigned)((unsigned<16>)Imm6)) ? X[rs1][15: 0] : ((unsigned<16>)Imm6);
X[rd][31:16] = ((unsigned)X[rs1][31:16] < (unsigned)((unsigned<16>)Imm6)) ? X[rs1][31:16] : ((unsigned<16>)Imm6);
}
}
}
CV_MINU_B {
encoding: 5'b00101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.minu.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)X[rs1][ 7: 0] < (unsigned)X[rs2][ 7: 0]) ? X[rs1][ 7: 0] : X[rs2][ 7: 0];
X[rd][15: 8] = ((unsigned)X[rs1][15: 8] < (unsigned)X[rs2][15: 8]) ? X[rs1][15: 8] : X[rs2][15: 8];
X[rd][23:16] = ((unsigned)X[rs1][23:16] < (unsigned)X[rs2][23:16]) ? X[rs1][23:16] : X[rs2][23:16];
X[rd][31:24] = ((unsigned)X[rs1][31:24] < (unsigned)X[rs2][31:24]) ? X[rs1][31:24] : X[rs2][31:24];
}
}
}
CV_MINU_SC_B {
encoding: 5'b00101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.minu.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)X[rs1][ 7: 0] < (unsigned)X[rs2][7:0]) ? X[rs1][ 7: 0] : X[rs2][7:0];
X[rd][15: 8] = ((unsigned)X[rs1][15: 8] < (unsigned)X[rs2][7:0]) ? X[rs1][15: 8] : X[rs2][7:0];
X[rd][23:16] = ((unsigned)X[rs1][23:16] < (unsigned)X[rs2][7:0]) ? X[rs1][23:16] : X[rs2][7:0];
X[rd][31:24] = ((unsigned)X[rs1][31:24] < (unsigned)X[rs2][7:0]) ? X[rs1][31:24] : X[rs2][7:0];
}
}
}
CV_MINU_SCI_B {
encoding: 5'b00101 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.minu.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)X[rs1][ 7: 0] < (unsigned)((unsigned<8>)Imm6)) ? X[rs1][ 7: 0] : ((unsigned<8>)Imm6);
X[rd][15: 8] = ((unsigned)X[rs1][15: 8] < (unsigned)((unsigned<8>)Imm6)) ? X[rs1][15: 8] : ((unsigned<8>)Imm6);
X[rd][23:16] = ((unsigned)X[rs1][23:16] < (unsigned)((unsigned<8>)Imm6)) ? X[rs1][23:16] : ((unsigned<8>)Imm6);
X[rd][31:24] = ((unsigned)X[rs1][31:24] < (unsigned)((unsigned<8>)Imm6)) ? X[rs1][31:24] : ((unsigned<8>)Imm6);
}
}
}
CV_MAX_H {
encoding: 5'b00110 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.max.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)X[rs1][15: 0] > (signed)X[rs2][15: 0]) ? X[rs1][15: 0] : X[rs2][15: 0];
X[rd][31:16] = ((signed)X[rs1][31:16] > (signed)X[rs2][31:16]) ? X[rs1][31:16] : X[rs2][31:16];
}
}
}
CV_MAX_SC_H {
encoding: 5'b00110 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.max.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)X[rs1][15: 0] > (signed)X[rs2][15:0]) ? X[rs1][15: 0] : X[rs2][15:0];
X[rd][31:16] = ((signed)X[rs1][31:16] > (signed)X[rs2][15:0]) ? X[rs1][31:16] : X[rs2][15:0];
}
}
}
CV_MAX_SCI_H {
encoding: 5'b00110 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.max.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)X[rs1][15: 0] > (signed)((unsigned<16>)((signed)Imm6))) ? X[rs1][15: 0] : ((unsigned<16>)((signed)Imm6));
X[rd][31:16] = ((signed)X[rs1][31:16] > (signed)((unsigned<16>)((signed)Imm6))) ? X[rs1][31:16] : ((unsigned<16>)((signed)Imm6));
}
}
}
CV_MAX_B {
encoding: 5'b00110 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.max.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)X[rs1][ 7: 0] > (signed)X[rs2][ 7: 0]) ? X[rs1][ 7: 0] : X[rs2][ 7: 0];
X[rd][15: 8] = ((signed)X[rs1][15: 8] > (signed)X[rs2][15: 8]) ? X[rs1][15: 8] : X[rs2][15: 8];
X[rd][23:16] = ((signed)X[rs1][23:16] > (signed)X[rs2][23:16]) ? X[rs1][23:16] : X[rs2][23:16];
X[rd][31:24] = ((signed)X[rs1][31:24] > (signed)X[rs2][31:24]) ? X[rs1][31:24] : X[rs2][31:24];
}
}
}
CV_MAX_SC_B {
encoding: 5'b00110 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.max.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)X[rs1][ 7: 0] > (signed)X[rs2][7:0]) ? X[rs1][ 7: 0] : X[rs2][7:0];
X[rd][15: 8] = ((signed)X[rs1][15: 8] > (signed)X[rs2][7:0]) ? X[rs1][15: 8] : X[rs2][7:0];
X[rd][23:16] = ((signed)X[rs1][23:16] > (signed)X[rs2][7:0]) ? X[rs1][23:16] : X[rs2][7:0];
X[rd][31:24] = ((signed)X[rs1][31:24] > (signed)X[rs2][7:0]) ? X[rs1][31:24] : X[rs2][7:0];
}
}
}
CV_MAX_SCI_B {
encoding: 5'b00110 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.max.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)X[rs1][ 7: 0] > (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][ 7: 0] : ((unsigned<8>)((signed)Imm6));
X[rd][15: 8] = ((signed)X[rs1][15: 8] > (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][15: 8] : ((unsigned<8>)((signed)Imm6));
X[rd][23:16] = ((signed)X[rs1][23:16] > (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][23:16] : ((unsigned<8>)((signed)Imm6));
X[rd][31:24] = ((signed)X[rs1][31:24] > (signed)((unsigned<8>)((signed)Imm6))) ? X[rs1][31:24] : ((unsigned<8>)((signed)Imm6));
}
}
}
CV_MAXU_H {
encoding: 5'b00111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.maxu.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)X[rs1][15: 0] > (unsigned)X[rs2][15: 0]) ? X[rs1][15: 0] : X[rs2][15: 0];
X[rd][31:16] = ((unsigned)X[rs1][31:16] > (unsigned)X[rs2][31:16]) ? X[rs1][31:16] : X[rs2][31:16];
}
}
}
CV_MAXU_SC_H {
encoding: 5'b00111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.maxu.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)X[rs1][15: 0] > (unsigned)X[rs2][15:0]) ? X[rs1][15: 0] : X[rs2][15:0];
X[rd][31:16] = ((unsigned)X[rs1][31:16] > (unsigned)X[rs2][15:0]) ? X[rs1][31:16] : X[rs2][15:0];
}
}
}
CV_MAXU_SCI_H {
encoding: 5'b00111 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.maxu.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((unsigned)X[rs1][15: 0] > (unsigned)((unsigned<16>)Imm6)) ? X[rs1][15: 0] : ((unsigned<16>)Imm6);
X[rd][31:16] = ((unsigned)X[rs1][31:16] > (unsigned)((unsigned<16>)Imm6)) ? X[rs1][31:16] : ((unsigned<16>)Imm6);
}
}
}
CV_MAXU_B {
encoding: 5'b00111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.maxu.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)X[rs1][ 7: 0] > (unsigned)X[rs2][ 7: 0]) ? X[rs1][ 7: 0] : X[rs2][ 7: 0];
X[rd][15: 8] = ((unsigned)X[rs1][15: 8] > (unsigned)X[rs2][15: 8]) ? X[rs1][15: 8] : X[rs2][15: 8];
X[rd][23:16] = ((unsigned)X[rs1][23:16] > (unsigned)X[rs2][23:16]) ? X[rs1][23:16] : X[rs2][23:16];
X[rd][31:24] = ((unsigned)X[rs1][31:24] > (unsigned)X[rs2][31:24]) ? X[rs1][31:24] : X[rs2][31:24];
}
}
}
CV_MAXU_SC_B {
encoding: 5'b00111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.maxu.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)X[rs1][ 7: 0] > (unsigned)X[rs2][7:0]) ? X[rs1][ 7: 0] : X[rs2][7:0];
X[rd][15: 8] = ((unsigned)X[rs1][15: 8] > (unsigned)X[rs2][7:0]) ? X[rs1][15: 8] : X[rs2][7:0];
X[rd][23:16] = ((unsigned)X[rs1][23:16] > (unsigned)X[rs2][7:0]) ? X[rs1][23:16] : X[rs2][7:0];
X[rd][31:24] = ((unsigned)X[rs1][31:24] > (unsigned)X[rs2][7:0]) ? X[rs1][31:24] : X[rs2][7:0];
}
}
}
CV_MAXU_SCI_B {
encoding: 5'b00111 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.maxu.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((unsigned)X[rs1][ 7: 0] > (unsigned)((unsigned<8>)Imm6)) ? X[rs1][ 7: 0] : ((unsigned<8>)Imm6);
X[rd][15: 8] = ((unsigned)X[rs1][15: 8] > (unsigned)((unsigned<8>)Imm6)) ? X[rs1][15: 8] : ((unsigned<8>)Imm6);
X[rd][23:16] = ((unsigned)X[rs1][23:16] > (unsigned)((unsigned<8>)Imm6)) ? X[rs1][23:16] : ((unsigned<8>)Imm6);
X[rd][31:24] = ((unsigned)X[rs1][31:24] > (unsigned)((unsigned<8>)Imm6)) ? X[rs1][31:24] : ((unsigned<8>)Imm6);
}
}
}
CV_SRL_H {
encoding: 5'b01000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.srl.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned)X[rs1][15: 0] >> (X[rs2][15: 0]);
X[rd][31:16] = (unsigned)X[rs1][31:16] >> (X[rs2][31:16]);
}
}
}
CV_SRL_SC_H {
encoding: 5'b01000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.srl.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned)X[rs1][15: 0] >> (X[rs2][15:0]);
X[rd][31:16] = (unsigned)X[rs1][31:16] >> (X[rs2][15:0]);
}
}
}
CV_SRL_SCI_H {
encoding: 5'b01000 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.srl.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned)X[rs1][15: 0] >> (((unsigned<16>)Imm6));
X[rd][31:16] = (unsigned)X[rs1][31:16] >> (((unsigned<16>)Imm6));
}
}
}
CV_SRL_B {
encoding: 5'b01000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.srl.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned)X[rs1][ 7: 0] >> (X[rs2][ 7: 0]);
X[rd][15: 8] = (unsigned)X[rs1][15: 8] >> (X[rs2][15: 8]);
X[rd][23:16] = (unsigned)X[rs1][23:16] >> (X[rs2][23:16]);
X[rd][31:24] = (unsigned)X[rs1][31:24] >> (X[rs2][31:24]);
}
}
}
CV_SRL_SC_B {
encoding: 5'b01000 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.srl.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned)X[rs1][ 7: 0] >> (X[rs2][7:0]);
X[rd][15: 8] = (unsigned)X[rs1][15: 8] >> (X[rs2][7:0]);
X[rd][23:16] = (unsigned)X[rs1][23:16] >> (X[rs2][7:0]);
X[rd][31:24] = (unsigned)X[rs1][31:24] >> (X[rs2][7:0]);
}
}
}
CV_SRL_SCI_B {
encoding: 5'b01000 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.srl.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned)X[rs1][ 7: 0] >> (((unsigned<8>)Imm6));
X[rd][15: 8] = (unsigned)X[rs1][15: 8] >> (((unsigned<8>)Imm6));
X[rd][23:16] = (unsigned)X[rs1][23:16] >> (((unsigned<8>)Imm6));
X[rd][31:24] = (unsigned)X[rs1][31:24] >> (((unsigned<8>)Imm6));
}
}
}
CV_SRA_H {
encoding: 5'b01001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sra.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned<16>)((signed)X[rs1][15: 0] >> (X[rs2][15: 0]));
X[rd][31:16] = (unsigned<16>)((signed)X[rs1][31:16] >> (X[rs2][31:16]));
}
}
}
CV_SRA_SC_H {
encoding: 5'b01001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sra.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned<16>)((signed)X[rs1][15: 0] >> (X[rs2][15:0]));
X[rd][31:16] = (unsigned<16>)((signed)X[rs1][31:16] >> (X[rs2][15:0]));
}
}
}
CV_SRA_SCI_H {
encoding: 5'b01001 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sra.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned<16>)((signed)X[rs1][15: 0] >> (((unsigned<16>)Imm6)));
X[rd][31:16] = (unsigned<16>)((signed)X[rs1][31:16] >> (((unsigned<16>)Imm6)));
}
}
}
CV_SRA_B {
encoding: 5'b01001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sra.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned<8>)((signed)X[rs1][ 7: 0] >> (X[rs2][ 7: 0]));
X[rd][15: 8] = (unsigned<8>)((signed)X[rs1][15: 8] >> (X[rs2][15: 8]));
X[rd][23:16] = (unsigned<8>)((signed)X[rs1][23:16] >> (X[rs2][23:16]));
X[rd][31:24] = (unsigned<8>)((signed)X[rs1][31:24] >> (X[rs2][31:24]));
}
}
}
CV_SRA_SC_B {
encoding: 5'b01001 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sra.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned<8>)((signed)X[rs1][ 7: 0] >> (X[rs2][7:0]));
X[rd][15: 8] = (unsigned<8>)((signed)X[rs1][15: 8] >> (X[rs2][7:0]));
X[rd][23:16] = (unsigned<8>)((signed)X[rs1][23:16] >> (X[rs2][7:0]));
X[rd][31:24] = (unsigned<8>)((signed)X[rs1][31:24] >> (X[rs2][7:0]));
}
}
}
CV_SRA_SCI_B {
encoding: 5'b01001 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sra.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned<8>)(signed)X[rs1][ 7: 0] >> (((unsigned<8>)Imm6));
X[rd][15: 8] = (unsigned<8>)(signed)X[rs1][15: 8] >> (((unsigned<8>)Imm6));
X[rd][23:16] = (unsigned<8>)(signed)X[rs1][23:16] >> (((unsigned<8>)Imm6));
X[rd][31:24] = (unsigned<8>)(signed)X[rs1][31:24] >> (((unsigned<8>)Imm6));
}
}
}
CV_SLL_H {
encoding: 5'b01010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sll.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned)X[rs1][15: 0] << (X[rs2][15: 0]);
X[rd][31:16] = (unsigned)X[rs1][31:16] << (X[rs2][31:16]);
}
}
}
CV_SLL_SC_H {
encoding: 5'b01010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sll.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned)X[rs1][15: 0] << (X[rs2][15:0]);
X[rd][31:16] = (unsigned)X[rs1][31:16] << (X[rs2][15:0]);
}
}
}
CV_SLL_SCI_H {
encoding: 5'b01010 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sll.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (unsigned)X[rs1][15: 0] << (((unsigned<16>)Imm6));
X[rd][31:16] = (unsigned)X[rs1][31:16] << (((unsigned<16>)Imm6));
}
}
}
CV_SLL_B {
encoding: 5'b01010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sll.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned)X[rs1][ 7: 0] << (X[rs2][ 7: 0]);
X[rd][15: 8] = (unsigned)X[rs1][15: 8] << (X[rs2][15: 8]);
X[rd][23:16] = (unsigned)X[rs1][23:16] << (X[rs2][23:16]);
X[rd][31:24] = (unsigned)X[rs1][31:24] << (X[rs2][31:24]);
}
}
}
CV_SLL_SC_B {
encoding: 5'b01010 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sll.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned)X[rs1][ 7: 0] << (X[rs2][7:0]);
X[rd][15: 8] = (unsigned)X[rs1][15: 8] << (X[rs2][7:0]);
X[rd][23:16] = (unsigned)X[rs1][23:16] << (X[rs2][7:0]);
X[rd][31:24] = (unsigned)X[rs1][31:24] << (X[rs2][7:0]);
}
}
}
CV_SLL_SCI_B {
encoding: 5'b01010 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.sll.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (unsigned)X[rs1][ 7: 0] << (((unsigned<8>)Imm6));
X[rd][15: 8] = (unsigned)X[rs1][15: 8] << (((unsigned<8>)Imm6));
X[rd][23:16] = (unsigned)X[rs1][23:16] << (((unsigned<8>)Imm6));
X[rd][31:24] = (unsigned)X[rs1][31:24] << (((unsigned<8>)Imm6));
}
}
}
CV_OR_H {
encoding: 5'b01011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.or.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] | X[rs2][15: 0])[15:0];
X[rd][31:16] = (X[rs1][31:16] | X[rs2][31:16])[15:0];
}
}
}
CV_OR_SC_H {
encoding: 5'b01011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.or.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] | X[rs2][15:0])[15:0];
X[rd][31:16] = (X[rs1][31:16] | X[rs2][15:0])[15:0];
}
}
}
CV_OR_SCI_H {
encoding: 5'b01011 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.or.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] | ((unsigned<16>)((signed)Imm6)))[15:0];
X[rd][31:16] = (X[rs1][31:16] | ((unsigned<16>)((signed)Imm6)))[15:0];
}
}
}
CV_OR_B {
encoding: 5'b01011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.or.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] | X[rs2][ 7: 0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] | X[rs2][15: 8])[7:0];
X[rd][23:16] = (X[rs1][23:16] | X[rs2][23:16])[7:0];
X[rd][31:24] = (X[rs1][31:24] | X[rs2][31:24])[7:0];
}
}
}
CV_OR_SC_B {
encoding: 5'b01011 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.or.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] | X[rs2][7:0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] | X[rs2][7:0])[7:0];
X[rd][23:16] = (X[rs1][23:16] | X[rs2][7:0])[7:0];
X[rd][31:24] = (X[rs1][31:24] | X[rs2][7:0])[7:0];
}
}
}
CV_OR_SCI_B {
encoding: 5'b01011 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.or.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] | ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][15: 8] = (X[rs1][15: 8] | ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][23:16] = (X[rs1][23:16] | ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][31:24] = (X[rs1][31:24] | ((unsigned<8>)((signed)Imm6)))[7:0];
}
}
}
CV_XOR_H {
encoding: 5'b01100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.xor.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] ^ X[rs2][15: 0])[15:0];
X[rd][31:16] = (X[rs1][31:16] ^ X[rs2][31:16])[15:0];
}
}
}
CV_XOR_SC_H {
encoding: 5'b01100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.xor.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] ^ X[rs2][15:0])[15:0];
X[rd][31:16] = (X[rs1][31:16] ^ X[rs2][15:0])[15:0];
}
}
}
CV_XOR_SCI_H {
encoding: 5'b01100 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.xor.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] ^ ((unsigned<16>)((signed)Imm6)))[15:0];
X[rd][31:16] = (X[rs1][31:16] ^ ((unsigned<16>)((signed)Imm6)))[15:0];
}
}
}
CV_XOR_B {
encoding: 5'b01100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.xor.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] ^ X[rs2][ 7: 0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] ^ X[rs2][15: 8])[7:0];
X[rd][23:16] = (X[rs1][23:16] ^ X[rs2][23:16])[7:0];
X[rd][31:24] = (X[rs1][31:24] ^ X[rs2][31:24])[7:0];
}
}
}
CV_XOR_SC_B {
encoding: 5'b01100 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.xor.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] ^ X[rs2][7:0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] ^ X[rs2][7:0])[7:0];
X[rd][23:16] = (X[rs1][23:16] ^ X[rs2][7:0])[7:0];
X[rd][31:24] = (X[rs1][31:24] ^ X[rs2][7:0])[7:0];
}
}
}
CV_XOR_SCI_B {
encoding: 5'b01100 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.xor.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] ^ ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][15: 8] = (X[rs1][15: 8] ^ ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][23:16] = (X[rs1][23:16] ^ ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][31:24] = (X[rs1][31:24] ^ ((unsigned<8>)((signed)Imm6)))[7:0];
}
}
}
CV_AND_H {
encoding: 5'b01101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.and.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] & X[rs2][15: 0])[15:0];
X[rd][31:16] = (X[rs1][31:16] & X[rs2][31:16])[15:0];
}
}
}
CV_AND_SC_H {
encoding: 5'b01101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.and.sc.h", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] & X[rs2][15:0])[15:0];
X[rd][31:16] = (X[rs1][31:16] & X[rs2][15:0])[15:0];
}
}
}
CV_AND_SCI_H {
encoding: 5'b01101 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.and.sci.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = (X[rs1][15: 0] & ((unsigned<16>)((signed)Imm6)))[15:0];
X[rd][31:16] = (X[rs1][31:16] & ((unsigned<16>)((signed)Imm6)))[15:0];
}
}
}
CV_AND_B {
encoding: 5'b01101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.and.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] & X[rs2][ 7: 0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] & X[rs2][15: 8])[7:0];
X[rd][23:16] = (X[rs1][23:16] & X[rs2][23:16])[7:0];
X[rd][31:24] = (X[rs1][31:24] & X[rs2][31:24])[7:0];
}
}
}
CV_AND_SC_B {
encoding: 5'b01101 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.and.sc.b", "{name(rd)}, {name(rs1)}, {name(rs2)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] & X[rs2][7:0])[7:0];
X[rd][15: 8] = (X[rs1][15: 8] & X[rs2][7:0])[7:0];
X[rd][23:16] = (X[rs1][23:16] & X[rs2][7:0])[7:0];
X[rd][31:24] = (X[rs1][31:24] & X[rs2][7:0])[7:0];
}
}
}
CV_AND_SCI_B {
encoding: 5'b01101 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.and.sci.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = (X[rs1][ 7: 0] & ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][15: 8] = (X[rs1][15: 8] & ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][23:16] = (X[rs1][23:16] & ((unsigned<8>)((signed)Imm6)))[7:0];
X[rd][31:24] = (X[rs1][31:24] & ((unsigned<8>)((signed)Imm6)))[7:0];
}
}
}
CV_ABS_H {
encoding: 5'b01110 :: 1'b0 :: 1'b0 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.abs.h", "{name(rd)}, {name(rs1)}" };
behavior: {
if (rd != 0) {
X[rd][15: 0] = ((signed)X[rs1][15: 0] < 0) ? (unsigned<16>)(-X[rs1][15: 0]) : X[rs1][15: 0];
X[rd][31:16] = ((signed)X[rs1][31:16] < 0) ? (unsigned<16>)(-X[rs1][31:16]) : X[rs1][31:16];
}
}
}
CV_ABS_B {
encoding: 5'b01110 :: 1'b0 :: 1'b0 :: 5'b00000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.abs.b", "{name(rd)}, {name(rs1)}" };
behavior: {
if (rd != 0) {
X[rd][ 7: 0] = ((signed)X[rs1][ 7: 0] < 0) ? (unsigned<8>)(-X[rs1][ 7: 0]) : X[rs1][ 7: 0];
X[rd][15: 8] = ((signed)X[rs1][15: 8] < 0) ? (unsigned<8>)(-X[rs1][15: 8]) : X[rs1][15: 8];
X[rd][23:16] = ((signed)X[rs1][23:16] < 0) ? (unsigned<8>)(-X[rs1][23:16]) : X[rs1][23:16];
X[rd][31:24] = ((signed)X[rs1][31:24] < 0) ? (unsigned<8>)(-X[rs1][31:24]) : X[rs1][31:24];
}
}
}
CV_EXTRACT_H {
encoding: 5'b10111 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.extract.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
unsigned<8> lower = Imm6[0]*16;
X[rd] = (unsigned<32>)((signed)X[rs1][lower+15 : lower ]);
}
}
}
CV_EXTRACT_B {
encoding: 5'b10111 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.extract.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
unsigned<8> lower = Imm6[1:0]*8;
X[rd] = (unsigned<32>)((signed)X[rs1][lower+7 :lower ]);
}
}
}
CV_EXTRACTU_H {
encoding: 5'b10111 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.extractu.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
unsigned<8> lower = Imm6[0]*16;
X[rd] = (unsigned<32>)(X[rs1][lower + 15 : lower ]);
}
}
}
CV_EXTRACTU_B {
encoding: 5'b10111 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.extractu.b", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
unsigned<8> lower = Imm6[1:0]*8;
X[rd] = (unsigned<32>)(X[rs1][lower + 7 : lower ]);
}
}
}
CV_INSERT_H {
encoding: 5'b10111 :: 1'b0 :: Imm6[0:0] :: Imm6[5:1] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011;
assembly: {"cv.insert.h", "{name(rd)}, {name(rs1)}, {Imm6}" };
behavior: {
if (rd != 0) {
unsigned<8> lower = Imm6[0]*16;
X[rd][lower + 15 : lower ] = X[rs1][15: 0];
}
}
}
CV_INSERT_B {