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/*
V
|
Zve64d
|
Zve64f
/ \
Zve64x Zve32f
\ /
Zve32x
Sections:
misa.v bit
eew in [8,16,32,64]
vlen >= 128
Configuration-Setting Instructions
Vector Load and Store Instructions
xlen=32 -> eew != 64
xlen=64:
Vector Integer Arithmetic Instructions
zve64* + eew=64 -> NO vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx (integer multiply variants that return the high word of the product)
Vector Fixed-point Arithmetic Instructions
zve64* + eew=64 -> NO vsmul.vv/vsmul.vx
Vector Single-Width Integer Reduction Instructions
Vector Widening Integer Reduction Instructions
Vector Mask Instructions
Vector Permutation Instructions
zve32x,zve64x -> NO floating-point scalar move instructions
Vector Floating-Point Instructions
eew=32
v,zve64d -> eew=64
v,zve64d -> +widening instructions/conversions(32->64)
Vector Single-Width Floating-Point reduction Instructions
eew=32
v,zve64d -> eew=64
v,zve64d -> +widening reductions(32->64)
*/
/*
*/
import "RVI.core_desc"
import "RISCVBase.core_desc"
InstructionSet RV32V extends RVV {
}
/*InstructionSet RV64V extends RV32V{}*/
InstructionSet RVV extends RVZve64d {
// What missing?
// -- Configuration-Setting Instructions
// -- Vector Load and Store Instructions
// -- Vector Integer Arithmetic Instructions
// -- Vector Fixed-point Arithmetic Instructions
// -- Vector Single-Width Integer Reduction Instructions
// -- Vector Widening Integer Reduction Instructions
// -- Vector Mask Instructions
// -- Vector Permutation Instructions
// -- Vector Floating-Point Instructions
// -- Vector Single-Width Floating-Point Reduction Instructions
// -- Vector Widening Floating-Point Reduction Instructions
// -- 2 Sort
}
InstructionSet RVZve64d extends RVZve64f {
// + double precision
// functions {
// bool validate_rvv() {
// unsigned<XLEN> _eew = vcfg_concatEEW(mew, width);
// return extension_enabled("V") && extension_enabled("F") && (_eew == 32 || _eew == 64);
// }
// }
// -- Configuration-Setting Instructions
// -- Vector Load and Store Instructions
// -- Vector Integer Arithmetic Instructions
// -- Vector Fixed-point Arithmetic Instructions
// -- Vector Single-Width Integer Reduction Instructions
// -- Vector Widening Integer Reduction Instructions
// -- Vector Mask Instructions
// -- Vector Permutation Instructions
// -- Vector Floating-Point Instructions
// v,zve64d -> eew=64
// v,zve64d -> +widening instructions/conversions(32->64)
// -- Vector Single-Width Floating-Point Reduction Instructions
// v,zve64d -> eew=64
// -- Vector Widening Floating-Point Reduction Instructions
// v,zve64d only
// -- 2 Sort
}
InstructionSet RVZve64f extends RVZve32f, RVZve64x {
// Ensure?
// functions {
// bool validate_rvv() {
// unsigned<XLEN> _eew = vcfg_concatEEW(mew, width);
// return extension_enabled("V") && extension_enabled("F") && (_eew == 32);
// }
// }
// -- Configuration-Setting Instructions
// -- Vector Load and Store Instructions
// -- Vector Integer Arithmetic Instructions
// -- Vector Fixed-point Arithmetic Instructions
// -- Vector Single-Width Integer Reduction Instructions
// -- Vector Widening Integer Reduction Instructions
// -- Vector Mask Instructions
// -- Vector Permutation Instructions
// -- Vector Floating-Point Instructions
// -- Vector Single-Width Floating-Point Reduction Instructions
// -- Vector Widening Floating-Point Reduction Instructions
// -- 2 Sort
}
InstructionSet RVZve32f extends RVZve32x, RV32F {
// + single precision
// functions {
// bool validate_rvv() {
// unsigned<XLEN> _eew = vcfg_concatEEW(mew, width);
// return extension_enabled("V") && extension_enabled("F") && _eew == 32;
// }
// }
// instructions [[enable=validate_rvv()]]{...}
functions {
// 13. Vector Floating-Point Instructions
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
extern unsigned<8> vfadd_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfadd_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfsub_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfsub_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfrsub_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
extern unsigned<8> vfwadd_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwadd_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfwsub_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwsub_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfwadd_wv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwadd_wf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfwsub_wv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwsub_wf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
extern unsigned<8> vfmul_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfmul_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfdiv_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfdiv_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfrdiv_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.5. Vector Widening Floating-Point Multiply
extern unsigned<8> vfwmul_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwmul_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
extern unsigned<8> vfmacc_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfmacc_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfnmacc_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfnmacc_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfmsac_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfmsac_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfnmsac_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfnmsac_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfmadd_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfmadd_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfnmadd_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfnmadd_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfmsub_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfmsub_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfnmsub_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfnmsub_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
extern unsigned<8> vfwmacc_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwmacc_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfwnmacc_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwnmacc_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfwmsac_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwmsac_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfwnmsac_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwnmsac_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.8. Vector Floating-Point Square-Root Instruction
extern unsigned<8> vfsqrt_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
extern unsigned<8> vfrsqrt7_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
extern unsigned<8> vfrec7_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 13.11. Vector Floating-Point MIN/MAX Instructions
extern unsigned<8> vfmin_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfmin_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfmax_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfmax_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.12. Vector Floating-Point Sign-Injection Instructions
extern unsigned<8> vfsgnj_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfsgnj_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfsgnjn_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfsgnjn_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vfsgnjx_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfsgnjx_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.13. Vector Floating-Point Compare Instructions
extern unsigned<8> vmfeq_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vmfeq_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vmfne_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vmfne_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vmflt_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vmflt_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vmfle_vv(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vmfle_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vmfgt_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
extern unsigned<8> vmfge_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN, unsigned<8> pRm);
// 13.14. Vector Floating-Point Classify Instruction
extern unsigned<8> vfclass_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 13.15. Vector Floating-Point Merge Instruction
extern unsigned<8> vfmerge_vfm(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN);
// 13.16. Vector Floating-Point Move Instruction
extern unsigned<8> vfmv_v_f(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVd, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pXLEN);
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
extern unsigned<8> vfcvt_xu_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfcvt_x_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfcvt_rtz_xu_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfcvt_rtz_x_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfcvt_f_xu_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfcvt_f_x_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
extern unsigned<8> vfwcvt_xu_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwcvt_x_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwcvt_rtz_xu_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwcvt_rtz_x_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwcvt_f_xu_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwcvt_f_x_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwcvt_f_f_v(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
extern unsigned<8> vfncvt_xu_f_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfncvt_x_f_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfncvt_rtz_xu_f_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfncvt_rtz_x_f_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfncvt_f_xu_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfncvt_f_x_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfncvt_f_f_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfncvt_rod_f_f_w(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 14. Vector Reduction Operations
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
extern unsigned<8> vfredosum_vs(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfredusum_vs(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfredmax_vs(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfredmin_vs(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 14.4. Vector Widening Floating-Point Reduction Instructions
extern unsigned<8> vfwredosum_vs(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
extern unsigned<8> vfwredusum_vs(void* pV, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs1, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pRm);
// 16.2. Floating-Point Scalar Move Instructions
extern unsigned<8> vfmv_f_s(void* pV, void* pF, unsigned<16> pVTYPE, unsigned<8> pRd, unsigned<8> pVs2, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pFLEN);
extern unsigned<8> vfmv_s_f(void* pV, void* pF, unsigned<16> pVTYPE, unsigned<8> pVd, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pFLEN);
// 16.3. Vector Slide Instructions
extern unsigned<8> vfslide1up_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pFLEN);
extern unsigned<8> vfslide1down_vf(void* pV, void* pR, unsigned<16> pVTYPE, unsigned<8> pVm, unsigned<8> pVd, unsigned<8> pVs2, unsigned<8> pRs1, unsigned<16> pVSTART, unsigned<32> pVLEN, unsigned<32> pVL, unsigned<8> pFLEN);
}
instructions {
// -- Configuration-Setting Instructions
// -- Vector Load and Store Instructions
// -- Vector Integer Arithmetic Instructions
// -- Vector Fixed-point Arithmetic Instructions
// -- Vector Single-Width Integer Reduction Instructions
// -- Vector Widening Integer Reduction Instructions
// -- Vector Mask Instructions
// -- Vector Permutation Instructions
// -- Vector Floating-Point Instructions
// 13. Vector Floating-Point Instructions
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
VFADD_VV {
encoding: 6'b000000 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfadd_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFADD_VF {
encoding: 6'b000000 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfadd_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFSUB_VV {
encoding: 6'b000010 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfsub_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFSUB_VF {
encoding: 6'b000010 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfsub_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFRSUB_VF {
encoding: 6'b100111 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfrsub_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
// End 13.2.
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
VFWADD_VV {
encoding: 6'b110000 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwadd_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWADD_VF {
encoding: 6'b110000 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwadd_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWSUB_VV {
encoding: 6'b110010 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwsub_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWSUB_VF {
encoding: 6'b110010 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwsub_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWADD_WV {
encoding: 6'b110100 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwadd_wv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWADD_WF {
encoding: 6'b110100 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwadd_wf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWSUB_WV {
encoding: 6'b110110 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwsub_wv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWSUB_WF {
encoding: 6'b110110 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwsub_wf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
// End 13.3.
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
VFMUL_VV {
encoding: 6'b100100 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmul_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFMUL_VF {
encoding: 6'b100100 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmul_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFDIV_VV {
encoding: 6'b100000 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfdiv_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFDIV_VF {
encoding: 6'b100000 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfdiv_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFRDIV_VF {
encoding: 6'b100001 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfrdiv_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
// End 13.4.
// 13.5. Vector Widening Floating-Point Multiply
VFWMUL_VV {
encoding: 6'b111000 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwmul_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFWMUL_VF {
encoding: 6'b111000 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfwmul_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
// End 13.5.
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
VFMACC_VV {
encoding: 6'b101100 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmacc_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFMACC_VF {
encoding: 6'b101100 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmacc_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFNMACC_VV {
encoding: 6'b101101 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfnmacc_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFNMACC_VF {
encoding: 6'b101101 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfnmacc_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFMSAC_VV {
encoding: 6'b101110 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmsac_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFMSAC_VF {
encoding: 6'b101110 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmsac_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFNMSAC_VV {
encoding: 6'b101111 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfnmsac_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFNMSAC_VF {
encoding: 6'b101111 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfnmsac_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFMADD_VV {
encoding: 6'b101000 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmadd_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFMADD_VF {
encoding: 6'b101000 :: vm[0:0] :: vs2[4:0] :: rs1[4:0] :: 3'b101 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfmadd_vf(V, F, _vtype, vm, vd, vs2, rs1, _vstart, _vlen, _vl, FLEN, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);
} else {
CSR[VSTART_ADDR] = 0;
}
unsigned<32> flags = fget_flags();
FCSR = (FCSR & ~FFLAG_MASK) | (flags & FFLAG_MASK);
}
}
VFNMADD_VV {
encoding: 6'b101001 :: vm[0:0] :: vs2[4:0] :: vs1[4:0] :: 3'b001 :: vd[4:0] :: 7'b1010111;
assembly:"{name(vd)}, {name(rs1)}, {name(vm)}";
behavior: {
unsigned<XLEN> _vtype = CSR[VTYPE_ADDR];
unsigned<XLEN> _vstart = CSR[VSTART_ADDR];
unsigned<XLEN> _vl = CSR[VL_ADDR];
unsigned<XLEN> _vlen = CSR[VLENB_ADDR]*8;
unsigned<XLEN> _rounding_mode = FCSR[7:5];
unsigned<XLEN> ret = vfnmadd_vv(V, _vtype, vm, vd, vs1, vs2, _vstart, _vlen, _vl, _rounding_mode);
if(ret != 0) {
CSR[VSTART_ADDR] = ret >> 8;
raise(0, 2);