Merge branch 'master' into sfrinaldi/02-doxygen-ci-fix

stefi07 · web-flow · commit f3162da9ff6b · 2026-04-02T13:42:56.000+01:00
diff --git a/.gitignore b/.gitignore
@@ -167,4 +167,6 @@ FineSteeringMirrorController/Liberopeekfifos/designer/FineSteeringMirror/user_se
 
 doxygen/*
 .vscode/*
-*.ctags
+*.ctags
+
+build/*
diff --git a/Makefile b/Makefile
@@ -0,0 +1,59 @@
+# Install headers from `include` directory into PREFIX directory.
+# By default, PREFIX is /usr/local/include/summerDevice, but it can be
+# overridden by setting the PREFIX variable when invoking make. For example:
+#   make install PREFIX=/opt/MAgAOX/source/summerDevice
+# Note: installing / uninstalling to /usr/local requires root privileges:
+#   sudo make install / uninstall
+
+PREFIX ?= /usr/local/include/summerDevice
+DESTDIR ?=
+
+SRCDIR := include
+BUILD_DIR := build
+MANIFEST := $(BUILD_DIR)/install_manifest.txt
+
+INSTALL_DIR := install -d
+
+ALL_HEADERS := $(shell find $(SRCDIR) -type f -name '*.h' -o -type f -name '*.hpp')
+
+.PHONY: all build install uninstall clean help
+
+# Default: build list of headers to be installed
+all: build
+
+build:
+	@echo "Building header list in $(BUILD_DIR)"
+	@mkdir -p $(BUILD_DIR)
+	@find $(SRCDIR) -type f -name '*.h' -o -type f -name '*.hpp' > $(BUILD_DIR)/headers.list
+	@echo "Found $$(wc -l < $(BUILD_DIR)/headers.list) header files to install"
+
+install: uninstall build
+	@echo "Installing headers to $(DESTDIR)$(PREFIX)"
+	@> $(MANIFEST)
+	@while IFS= read -r f; do \
+		rel=$${f#$(SRCDIR)/}; \
+		dest=$(DESTDIR)$(PREFIX)/$$rel; \
+		$(INSTALL_DIR) "$$(dirname "$$dest")"; \
+		cp "$$f" "$$dest"; \
+		echo "$$dest" >> $(MANIFEST); \
+	done < $(BUILD_DIR)/headers.list
+	@echo "Installed $$(wc -l < $(MANIFEST)) headers; manifest written to $(MANIFEST)"
+
+uninstall:
+	@if [ -f $(MANIFEST) ]; then \
+		echo "Removing files listed in $(MANIFEST)"; \
+		xargs rm -f < $(MANIFEST); \
+		rm -f $(MANIFEST); \
+		echo "Removing empty directories under $(DESTDIR)$(PREFIX)"; \
+		find $(DESTDIR)$(PREFIX) -type d -empty -delete 2>/dev/null || true; \
+	else \
+		echo "No manifest found at $(MANIFEST); nothing to uninstall"; \
+	fi
+
+clean:
+	@echo "Cleaning $(BUILD_DIR)"
+	@rm -rf $(BUILD_DIR)
+
+help:
+	@echo "Usage: make [target] [PREFIX=/path] [DESTDIR=/staging]"
+	@echo "Targets: all, build, install, uninstall, clean, help"
diff --git a/include/fpga/FieldLatcher.vhd b/include/fpga/FieldLatcher.vhd
@@ -0,0 +1,76 @@
+--
+--           Copyright (c) by Franks Development, LLC
+--
+-- This software is copyrighted by and is the sole property of Franks
+-- Development, LLC. All rights, title, ownership, or other interests
+-- in the software remain the property of Franks Development, LLC. This
+-- software may only be used in accordance with the corresponding
+-- license agreement.  Any unauthorized use, duplication, transmission,
+-- distribution, or disclosure of this software is expressly forbidden.
+--
+-- This Copyright notice may not be removed or modified without prior
+-- written consent of Franks Development, LLC.
+--
+-- Franks Development, LLC. reserves the right to modify this software
+-- without notice.
+--
+-- Franks Development, LLC            support@franks-development.com
+-- 500 N. Bahamas Dr. #101           http:--www.franks-development.com
+-- Tucson, AZ 85710
+-- USA
+--
+-- Permission granted for perpetual non-exclusive end-use by the University of Arizona August 1, 2020
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+library work;
+use work.CGraphTypes.all;
+
+entity FieldLatcher is
+  port (
+		clk : in std_logic;
+		rst : in std_logic;
+			
+		-- Bus:
+		ByteIn : in std_logic_vector(7 downto 0);
+		WriteReq : in std_logic;
+		FieldLatched : out std_logic_vector(31 downto 0)--;
+  );
+end FieldLatcher;
+
+
+architecture FieldLatcherImplemenatation of FieldLatcher is
+	
+	signal LastWriteReq : std_logic;
+	
+  begin
+  process (clk, rst)
+  begin
+  	
+    if (rst = '1') then
+      
+		LastWriteReq <= '0';
+		FieldLatched <= x"00000000";
+		
+    else
+	
+      if ( (clk'event) and (clk = '1') ) then
+
+	    LastWriteReq <= WriteReq;
+	  
+        if ( (LastWriteReq = '0') and (WriteReq = '1') ) then
+		
+			FieldLatched(31 downto 24) <= FieldLatched(23 downto 16);
+			FieldLatched(23 downto 16) <= FieldLatched(15 downto 8);
+			FieldLatched(15 downto 8) <= FieldLatched(7 downto 0);
+			FieldLatched(7 downto 0) <= ByteIn;
+			
+		end if;
+  	  end if;  
+    end if;
+  end process;
+
+end FieldLatcherImplemenatation;
+
diff --git a/include/fpga/PeekRingBuffer.vhd b/include/fpga/PeekRingBuffer.vhd
@@ -38,6 +38,11 @@ entity PeekRingBuffer is
 	DataEndAddress : out std_logic_vector(PeekRamDepth - 1 downto 0);
     PeekAddress : in std_logic_vector(PeekRamDepth - 1 downto 0);
     PopAddress : in std_logic_vector(PeekRamDepth - 1 downto 0);
+    LastHeaderEnd : out std_logic_vector(PeekRamDepth - 1 downto 0);
+	LastFooterEnd : out std_logic_vector(PeekRamDepth - 1 downto 0);
+    PopAddress : in std_logic_vector(PeekRamDepth - 1 downto 0);
+	PayloadLen : out std_logic_vector(31 downto 0);
+	HeaderFooterPayloadLenMatches : out std_logic;
     ByteIn : in std_logic_vector(7 downto 0);
     ByteOut : out std_logic_vector(7 downto 0);
     WriteReq : in std_logic;
@@ -68,11 +73,49 @@ architecture PeekRingBufferImplemenatation of PeekRingBuffer is
 	  );
 	end component;
 	
+	component PatternFinder is
+	  generic (
+		Byte0 : std_logic_vector(7 downto 0) := x"00";
+		Byte1 : std_logic_vector(7 downto 0) := x"00";
+		Byte2 : std_logic_vector(7 downto 0) := x"00";
+		Byte3 : std_logic_vector(7 downto 0) := x"00"--;
+	  );
+	  port (
+		clk : in std_logic;
+		rst : in std_logic;
+			
+		-- Bus:
+		ByteIn : in std_logic_vector(7 downto 0);
+		WriteReq : in std_logic;
+		Found : out std_logic--;
+	  );
+	end component;
+	
+	component FieldLatcher is
+	  port (
+		clk : in std_logic;
+		rst : in std_logic;
+			
+		-- Bus:
+		ByteIn : in std_logic_vector(7 downto 0);
+		WriteReq : in std_logic;
+		FieldLatched : out std_logic_vector(31 downto 0)--;
+	  );
+	end component;
+
+
 	signal DataStartAddress_i : std_logic_vector(PeekRamDepth - 1 downto 0);
 	signal WriteAddress : std_logic_vector(PeekRamDepth - 1 downto 0);
 
 	signal LastPopReq : std_logic;
 	signal LastWriteReq : std_logic;
+
+	signal HeaderFound : std_logic;
+	signal FooterFound : std_logic;
+	signal LastHeaderFound : std_logic;
+	signal LastFooterFound : std_logic;
+	
+	signal MaybePayloadLen : std_logic_vector(31 downto 0);
 	
   begin
   
@@ -88,6 +131,50 @@ architecture PeekRingBufferImplemenatation of PeekRingBuffer is
 		WriteReq => WriteReq
 	);
 	
+	HeaderFinder : PatternFinder
+	generic map 
+	(
+		Byte0 => x"1B",
+		Byte1 => x"AD",
+		Byte2 => x"BA",
+		Byte3 => x"BE"--,
+	);
+	port map
+	(
+		clk => clk,
+		rst => rst,
+		ByteIn => ByteIn,
+		WriteReq => WriteReq,
+		Found => HeaderFound--,
+	);
+	
+	FooterFinder : PatternFinder
+	generic map 
+	(
+		Byte0 => x"0A",
+		Byte1 => x"0F",
+		Byte2 => x"AD",
+		Byte3 => x"ED"--,
+	);
+	port map
+	(
+		clk => clk,
+		rst => rst,
+		ByteIn => ByteIn,
+		WriteReq => WriteReq,
+		Found => FooterFound--,
+	);
+	
+	PayloadLenLatcher : FieldLatcher
+	port map 
+	(
+		clk => clk,
+		rst => rst,
+		ByteIn => ByteIn,
+		WriteReq => WriteReq,
+		FieldLatched => MaybePayloadLen--,
+	);
+	
   process (clk, rst)
   begin
   
@@ -114,12 +201,17 @@ architecture PeekRingBufferImplemenatation of PeekRingBuffer is
 		LastWriteReq <= '0';
 		DataStartAddress_i <= (others => '0');
 		WriteAddress <= (others => '0');
+		LastHeaderEnd <= (others => '0');
+		LastFooterEnd <= (others => '0');
+		PayloadLen <= x"00000000";
         
     else
       if ( (clk'event) and (clk = '1') ) then
 
 	    LastPopReq <= PopReq;
 	    LastWriteReq <= WriteReq;
+		LastHeaderFound <= HeaderFound;
+		LastFooterFound <= FooterFound;
 	  
         if ( (LastPopReq = '0') and (PopReq = '1') ) then
 		
@@ -133,21 +225,68 @@ architecture PeekRingBufferImplemenatation of PeekRingBuffer is
 				
 			if (WriteAddress < ( (2**PeekRamDepth) - 1) ) then
 		
-				--~ WriteAddress <= WriteAddress + std_logic_vector(to_unsigned(1, PeekRamDepth));
-				WriteAddress <= WriteAddress + "0000000001";
+				WriteAddress <= WriteAddress + std_logic_vector(to_unsigned(1, PeekRamDepth));
+				--~ WriteAddress <= WriteAddress + "0000000001";
 				
 			else --wrap
 			
 				WriteAddress <= (others => '0');
 				
 			end if;
-        
+			
+			--If we wrap footer or header, clear!
+			if (LastHeaderEnd = WriteAddress + "0000000001") then LastHeaderEnd <= (others => '0'); end if;
+			
+			if (LastFooterEnd = WriteAddress + "0000000001") then LastFooterEnd <= (others => '0'); end if;
+			
+			--Grab the payload len?
+			
+			if (WriteAddress >= LastHeaderEnd) then
+			
+				if (WriteAddress = (LastHeaderEnd + 3) then PayloadLen <= MaybePayloadLen; end if;
+			
+			else
+
+				if (WriteAddress = (LastHeaderEnd + 3 - (2**PeekRamDepth)) then PayloadLen <= MaybePayloadLen; end if; --!!!this calc is WRONG!!! Needs to WRAP correctly...
+			
+			end if;
+			
 		else
 		
 			Dbg1 <= '0';
 			
 		end if;
 
+		--Update on the edge of found; can't put this on the writereq edge, because the flag will toggle on the next clock after, not synchrounously!
+		if ( (LastHeaderFound = '0') and (HeaderFound = '1') ) then LastHeaderEnd = WriteAddress - "0000000001"; end if;
+		
+		if ( (LastFooterFound = '0') and (FooterFound = '1') ) then 
+		
+			LastFooterEnd = WriteAddress - "0000000001"; 
+			
+			--Found a footer! This should initiate more checks; namely, generating & testing the CRC and checking if headerpos +length <+appropriate offsets> = footerpos
+				--Really need to test & fix CRCer first...
+					--~ RS422_Rx0_Crcer : CrcFifo
+					--~ generic map
+					--~ (
+						--~ DEPTH_BITS => 10--,
+					--~ )
+					--~ port map
+					--~ (
+						--~ clk => MasterClk,
+						--~ rst => Uart0DoCrc,
+						--~ FifoStartAddr => Uart0CrcStartAddr,
+						--~ FifoEndAddr => Uart0CrcEndAddr,
+						--~ FifoPeekData => Uart0RxFifoPeekPeekData,
+						--~ FifoPeekAddr => Uart0RxFifoPeekPeekAddrCrcer,
+						--~ Crc => Uart0Crc,
+						--~ CrcComplete => Uart0CrcDone--,
+					--~ );
+
+			--~ HeaderFooterPayloadLenMatches <=
+        
+		end if;
+		
   	  end if;  
     end if;
   end process;
