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docs/Generators/TestChipIP.rst
@@ -118,4 +118,4 @@ for examples of configs with CTC.
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By default, CTC uses the credited PHY provided with the Serial TileLink interface (see
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:ref:`Generators/TestChipIP:TileLink SERDES`). CTC can also be instantiated without a PHY. The
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intended use for this mode is for multi-chiplet FireSim simulations using the CTC bridge. For
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-more information on FireSim, see :ref:`Simulation/FPGA-Accelerated Simulation:FireSim`.
+more information on FireSim, see :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim`.
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