Merge pull request #2234 from ucb-bar/tacit-bp

ADD: branch predictor mode support for tacit

Author: iansseijelly

build.sbt

@@ -265,7 +265,7 @@ lazy val nvdla = (project in file("generators/nvdla"))
   .settings(commonSettings)
 
 lazy val tacit = (project in file("generators/tacit"))
-  .dependsOn(rocketchip, shuttle)
+  .dependsOn(rocketchip, shuttle, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -14,7 +14,6 @@ import freechips.rocketchip.devices.tilelink._
 
 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
-  with tacit.CanHaveTraceSinkDMA
   with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
   with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
   with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -15,8 +15,9 @@ import vexiiriscv.{VexiiRiscvTileAttachParams}
 import testchipip.cosim.{TracePortKey, TracePortParams}
 import barf.{TilePrefetchingMasterPortParams}
 import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams}
-import tacit.{TacitEncoder}
+import tacit.{TacitEncoder, TacitBPParams}
 import shuttle.common.{ShuttleTileAttachParams}
+
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -78,8 +79,9 @@ class WithTacitEncoder extends Config((site, here, up) => {
           xlen = tp.tileParams.core.xLen,
           iaddrWidth = tp.tileParams.core.xLen
         ), 
-        bufferDepth = 16,
-        coreStages = 5)(p)),
+        bufferDepth = 16, 
+        coreStages = 5, 
+        bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
         useArbiterMonitor = false
       )),
       core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
@@ -90,7 +92,10 @@ class WithTacitEncoder extends Config((site, here, up) => {
           nGroups = tp.tileParams.core.retireWidth,
           xlen = tp.tileParams.core.xLen,
           iaddrWidth = tp.tileParams.core.xLen
-        ), bufferDepth = 16, coreStages = 7)(p)),
+        ), 
+        bufferDepth = 16, 
+        coreStages = 7, 
+        bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
         useArbiterMonitor = false
       )),
       core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))