Add experimental chisel7 support

Author: jerryz123

build.sbt

@@ -1,6 +1,7 @@
 import Tests._
 
 val chisel6Version = "6.7.0"
+val chisel7Version = "7.0.0-RC4"
 val chiselTestVersion = "6.0.0"
 val scalaVersionFromChisel = "2.13.16"
 
@@ -92,12 +93,17 @@ lazy val chisel6Settings = Seq(
   libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % chisel6Version),
   addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chisel6Version cross CrossVersion.full)
 )
+lazy val chisel7Settings = Seq(
+  libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % chisel7Version),
+  addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chisel7Version cross CrossVersion.full)
+)
 lazy val chisel3Settings = Seq(
   libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chisel3Version),
   addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chisel3Version cross CrossVersion.full)
 )
 
-lazy val chiselSettings = chisel6Settings ++ Seq(
+// Select Chisel 7 when USE_CHISEL7 is set in the environment; default to Chisel 6.
+lazy val chiselSettings = (if (sys.env.contains("USE_CHISEL7")) chisel7Settings else chisel6Settings) ++ Seq(
   libraryDependencies ++= Seq(
     "org.apache.commons" % "commons-lang3" % "3.12.0",
     "org.apache.commons" % "commons-text" % "1.9"
@@ -115,11 +121,17 @@ lazy val scalaTestSettings =  Seq(
 
 // -- Rocket Chip --
 
-lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
-  .settings(chiselSettings)
-  .settings(commonSettings)
-  .dependsOn(midas_target_utils)
-  .settings(scalaTestSettings)
+lazy val hardfloat = {
+  val useChisel7 = sys.env.contains("USE_CHISEL7")
+  var hf = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
+    .settings(chiselSettings)
+    .settings(commonSettings)
+    .settings(scalaTestSettings)
+  if (!useChisel7) {
+    hf = hf.dependsOn(midas_target_utils)
+  }
+  hf
+}
 
 lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(commonSettings)
@@ -154,24 +166,55 @@ lazy val testchipip = withInitCheck((project in file("generators/testchipip")),
   .settings(commonSettings)
 
 lazy val chipyard = {
+  val useChisel7 = sys.env.contains("USE_CHISEL7")
   // Base chipyard project with always-on dependencies
   // Use explicit Project(...) so the project id remains 'chipyard'
-  var cy = Project(id = "chipyard", base = file("generators/chipyard"))
-    .dependsOn(
+  val baseProjects: Seq[ProjectReference] =
+    Seq(
       testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
-      dsptools, rocket_dsp_utils,
       icenet, tracegen,
       constellation, barf, shuttle, rerocc,
-      firrtl2_bridge
-    )
+    ).map(sbt.Project.projectToRef) ++
+    (if (useChisel7) Seq() else Seq(sbt.Project.projectToRef(firrtl2_bridge))) ++
+    (if (useChisel7) Seq() else Seq(sbt.Project.projectToRef(dsptools), sbt.Project.projectToRef(rocket_dsp_utils)))
+
+  val baseDeps: Seq[sbt.ClasspathDep[sbt.ProjectReference]] =
+    baseProjects.map(pr => sbt.ClasspathDependency(pr, None))
+
+  // Optional settings to exclude specific sources under Chisel 7
+  val dspExcludeSettings: Seq[Def.Setting[_]] = if (useChisel7) Seq(
+    Compile / unmanagedSources := {
+      val files = (Compile / unmanagedSources).value
+      val root = (ThisBuild / baseDirectory).value
+      val excludeList = Seq(
+        // Directories or files relative to repo root
+        "generators/chipyard/src/main/scala/example/dsptools",
+        "generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala",
+        "generators/chipyard/src/main/scala/config/TutorialConfigs.scala",
+        "generators/chipyard/src/main/scala/upf"
+      ).map(p => (root / p).getCanonicalFile)
+      val (excludeDirs, excludeFiles) = excludeList.partition(_.isDirectory)
+      files.filterNot { f =>
+        val cf = f.getCanonicalFile
+        excludeFiles.contains(cf) || excludeDirs.exists(d => cf.toPath.startsWith(d.toPath))
+      }
+    }
+  ) else Seq.empty
+
+  var cy = Project(id = "chipyard", base = file("generators/chipyard"))
+    .dependsOn(baseDeps: _*)
     .settings(libraryDependencies ++= rocketLibDeps.value)
     .settings(
       libraryDependencies ++= Seq(
         "org.reflections" % "reflections" % "0.10.2"
       )
     )
     .settings(commonSettings)
-    .settings(Compile / unmanagedSourceDirectories += file("tools/stage/src/main/scala"))
+    .settings(Compile / unmanagedSourceDirectories += {
+      if (useChisel7) file("tools/stage-chisel7/src/main/scala")
+      else file("tools/stage/src/main/scala")
+    })
+    .settings(dspExcludeSettings: _*)
 
   // Optional modules discovered via initialized submodules (no env or manifest)
   val optionalModules: Seq[(String, ProjectReference)] = Seq(

common.mk

@@ -16,6 +16,21 @@ define require_cmd
 		|| { echo "Error: $(1) not found in PATH. Set up your tool environment before building this target." >&2; exit 1; }
 endef
 
+# Require minimum firtool version when building with Chisel 7
+define require_firtool_version
+	@if [ -n "$(USE_CHISEL7)" ]; then \
+	  vline=`$(FIRTOOL_BIN) --version 2>/dev/null | grep -E 'CIRCT firtool-[0-9]+\.[0-9]+\.[0-9]+' | head -1`; \
+	  vstr=$${vline##*firtool-}; \
+	  if [ -z "$$vstr" ]; then \
+	    echo "Error: Unable to parse firtool version. Ensure '$(FIRTOOL_BIN) --version' prints 'CIRCT firtool-X.Y.Z'." >&2; exit 1; \
+	  fi; \
+	  maj=$${vstr%%.*}; rest=$${vstr#*.}; min=$${rest%%.*}; pat=$${rest#*.}; \
+	  if [ "$$maj" -lt 1 ] || { [ "$$maj" -eq 1 ] && [ "$$min" -lt 129 ]; }; then \
+	    echo "Error: USE_CHISEL7 requires firtool >= 1.129.0, found $$vstr. Please update CIRCT firtool." >&2; exit 1; \
+	  fi; \
+	fi
+endef
+
 #########################################################################################
 # specify user-interface variables
 #########################################################################################
@@ -160,6 +175,9 @@ export mfc_extra_anno_contents
 export sfc_extra_low_transforms_anno_contents
 $(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE)
 	echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE)
+ifdef USE_CHISEL7
+	jq '. + [{"class":"firrtl.transforms.BlackBoxTargetDirAnno","targetDir":"$(GEN_COLLATERAL_DIR)/blackboxes"}]' $(MFC_EXTRA_ANNO_FILE) > $(MFC_EXTRA_ANNO_FILE).tmp && mv $(MFC_EXTRA_ANNO_FILE).tmp $(MFC_EXTRA_ANNO_FILE)
+endif
 	jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE)
 
 .PHONY: firrtl
@@ -180,6 +198,12 @@ SFC_MFC_TARGETS = \
 
 MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket
 
+# Extra firtool flags are only applied when building with Chisel 7
+FIRTOOL_EXTRA_FLAGS ?=
+ifdef USE_CHISEL7
+FIRTOOL_EXTRA_FLAGS += --verification-flavor=if-else-fatal
+endif
+
 # DOC include start: FirrtlCompiler
 $(MFC_LOWERING_OPTIONS):
 	mkdir -p $(dir $@)
@@ -191,6 +215,7 @@ endif
 
 $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
 	$(call require_cmd,$(FIRTOOL_BIN))
+	$(require_firtool_version)
 	rm -rf $(GEN_COLLATERAL_DIR)
 	(set -o pipefail && $(FIRTOOL_BIN) \
 			--format=fir \
@@ -205,12 +230,29 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
 			--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
 			--annotation-file=$(FINAL_ANNO_FILE) \
 			--split-verilog \
+			$(FIRTOOL_EXTRA_FLAGS) \
 			-o $(GEN_COLLATERAL_DIR) \
 			$(FIRRTL_FILE) |& tee $(FIRTOOL_LOG_FILE))
 	$(SED) $(SED_INPLACE) 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
-	touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
+ifdef USE_CHISEL7
+	# Construct blackbox file list from files emitted into gen-collateral/blackboxes
+	@if [ -d "$(GEN_COLLATERAL_DIR)/blackboxes" ]; then \
+	  find "$(GEN_COLLATERAL_DIR)/blackboxes" -type f \( -name '*.v' -o -name '*.sv' -o -name '*.cc' \) | \
+	    sed -e 's;^$(GEN_COLLATERAL_DIR)/;;' > "$(MFC_BB_MODS_FILELIST)"; \
+	else \
+	  : > "$(MFC_BB_MODS_FILELIST)"; \
+	fi
+else
+	# If there are no BB's then the file might not be generated; ensure it exists
+	touch $(MFC_BB_MODS_FILELIST)
+endif
 # DOC include end: FirrtlCompiler
 
+.PHONY: run-firtool
+run-firtool: $(SFC_MFC_TARGETS)
+	@echo "[run-firtool] Generated: $(SFC_MFC_TARGETS)"
+
+
 $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_TOP_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST)
 	$(base_dir)/scripts/uniquify-module-names.py \
 		--model-hier-json $(MFC_MODEL_HRCHY_JSON) \

scripts/uniquify-module-names.py

@@ -5,6 +5,7 @@
 import shutil
 import os
 import sys
+import platform
 
 
 parser = argparse.ArgumentParser(description="")
@@ -23,6 +24,8 @@
 
 MODEL_SFX=args.model + "_UNIQUIFIED"
 SED=os.environ.get("SED", "sed")
+# macOS/BSD sed requires an explicit suffix for -i; use empty suffix
+SED_INPLACE = "-i ''" if platform.system() == "Darwin" else "-i"
 
 
 def bash(cmd):
@@ -63,15 +66,17 @@ def get_modules_in_filelist(filelist, verilog_module_filename, cc_filelist):
     lines = fl.readlines()
     for line in lines:
       path = line.strip()
-      basepath = os.path.basename(path)
-      ext = basepath.split(".")[-1]
+      # Preserve relative directories in the filelist; 'path' is relative to args.gcpath
+      ext = os.path.basename(path).split(".")[-1]
 
       if (ext == "v") or (ext == "sv"):
-        modules = get_modules_in_verilog_file(os.path.join(args.gcpath, basepath))
+        modules = get_modules_in_verilog_file(os.path.join(args.gcpath, path))
         for module in modules:
-          verilog_module_filename[module] = basepath
+          # Map module name to its relative path under gcpath
+          verilog_module_filename[module] = path
       else:
-        cc_filelist.append(basepath)
+        # Track non-Verilog sidecar files with their relative paths
+        cc_filelist.append(path)
   return (verilog_module_filename, cc_filelist)
 
 def get_modules_under_hier(hier, child_to_ignore=None):
@@ -87,10 +92,11 @@ def write_verilog_filelist(modules, verilog_module_filename, out_filelist):
   with open(out_filelist, "w") as df:
     for module in modules:
       if module in existing_modules:
-        verilog_filename = verilog_module_filename[module]
+        verilog_filename = verilog_module_filename[module]  # relative to gcpath
         if verilog_filename not in written_files:
           written_files.add(verilog_filename)
-          if args.target_dir in verilog_filename:
+          # Always prefix with target_dir unless the path is already absolute
+          if os.path.isabs(verilog_filename):
             df.write(f"{verilog_filename}\n")
           else:
             df.write(f"{args.target_dir}/{verilog_filename}\n")
@@ -99,20 +105,31 @@ def write_verilog_filelist(modules, verilog_module_filename, out_filelist):
 def write_cc_filelist(filelist, out_filelist):
   with open(out_filelist, "a") as df:
     for path in filelist:
-      file = os.path.basename(path)
-      df.write(f"{args.target_dir}/{file}\n")
+      # Preserve relative layout for non-Verilog files as well
+      if os.path.isabs(path):
+        df.write(f"{path}\n")
+      else:
+        df.write(f"{args.target_dir}/{path}\n")
+
+def generate_copy(rel_path, sfx):
+  # rel_path is the file path relative to args.gcpath, e.g., 'verification/assert/Foo.sv'
+  dirname = os.path.dirname(rel_path)
+  basename = os.path.basename(rel_path)
+  (base_no_ext, ext) = os.path.splitext(basename)
 
-def generate_copy(c, sfx):
-  (cur_name, ext) = os.path.splitext(c)
-  new_name = cur_name + "_" + sfx
-  new_file = new_name + ext
+  # New module/file name with suffix, preserving directory structure
+  new_basename = base_no_ext + "_" + sfx
+  new_rel_path = os.path.join(dirname, new_basename + ext) if dirname else (new_basename + ext)
 
-  cur_file = os.path.join(args.gcpath, c)
-  new_file = os.path.join(args.gcpath, new_file)
+  cur_abs = os.path.join(args.gcpath, rel_path)
+  new_abs = os.path.join(args.gcpath, new_rel_path)
 
-  shutil.copy(cur_file, new_file)
-  bash(rf"{SED} -i 's/module\( \+\){cur_name}/module\1{new_name}/' {new_file}")
-  return new_file
+  os.makedirs(os.path.dirname(new_abs) or args.gcpath, exist_ok=True)
+  shutil.copy(cur_abs, new_abs)
+  # Update module declaration inside the copied file
+  bash(rf"{SED} {SED_INPLACE} -e 's/module\( \+\){base_no_ext}/module\1{new_basename}/' {new_abs}")
+  # Return the new file path relative to gcpath
+  return new_rel_path
 
 def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
   q = [(tree['instance_name'], tree['module_name'], tree['instances'], None)]
@@ -138,7 +155,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
         new_file = generate_copy(cur_file, MODEL_SFX)
         if parent is not None and ((parent, mod) not in updated_submodule):
           parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
-          bash(rf"{SED} -i 's/\( \*\){mod}\( \+\)/\1{mod}_{MODEL_SFX}\2/' {parent_file}")
+          bash(rf"{SED} {SED_INPLACE} -e 's/\( \*\){mod}\( \+\)/\1{mod}_{MODEL_SFX}\2/' {parent_file}")
           updated_submodule.add((parent, mod))
 
         # add the uniquified module to the verilog_modul_filename dict

tools/stage-chisel7/src/main/scala/ChipyardAnnotations.scala

@@ -0,0 +1,79 @@
+// See LICENSE for license details.
+// Based on Rocket Chip's stage implementation
+
+package chipyard.stage
+
+import chisel3.experimental.BaseModule
+import firrtl.annotations.{Annotation, NoTargetAnnotation}
+import firrtl.options.{HasShellOptions, ShellOption, Unserializable}
+
+trait ChipyardOption extends Unserializable { this: Annotation => }
+
+/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format  */
+private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "legacy-configs",
+      toAnnotationSeq = a => {
+        val split = a.split(':')
+        assert(split.length == 2, s"'${a}' split by ':' doesn't yield two things")
+        val packageName = split.head
+        val configs     = split.last.split("_")
+        Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } ))
+      },
+      helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).",
+      shortOption = Some("LC")
+    )
+  )
+}
+
+/** Paths to config classes */
+case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object ConfigsAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[Seq[String]](
+      longOption = "configs",
+      toAnnotationSeq = a => Seq(ConfigsAnnotation(a)),
+      helpText = "<comma-delimited configs>",
+      shortOption = Some("C")
+    )
+  )
+}
+
+case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with ChipyardOption
+private[stage] object TopModuleAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "top-module",
+      toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])),
+      helpText = "<top module>",
+      shortOption = Some("T")
+    )
+  )
+}
+
+/** Optional base name for generated files' filenames */
+case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with ChipyardOption
+private[stage] object OutputBaseNameAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[String](
+      longOption = "name",
+      toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)),
+      helpText = "<base name of output files>",
+      shortOption = Some("n")
+    )
+  )
+}
+
+/** Optionally generate legacy FIRRTL2 SFC FIRRTL generation */
+case class LegacySFCAnnotation() extends NoTargetAnnotation with ChipyardOption
+private[stage] object LegacySFCAnnotation extends HasShellOptions {
+  override val options = Seq(
+    new ShellOption[Unit](
+      longOption = "emit-legacy-sfc",
+      toAnnotationSeq = a => Seq(LegacySFCAnnotation()),
+      helpText = "Emit a legacy FIRRTL2 SFC FIRRTL file",
+      shortOption = Some("els")
+    )
+  )
+}