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jerryz123jerryz123
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Modularize out cores
1 parent 88b0ad7 commit 2cf2e18

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6 files changed

+103
-71
lines changed

6 files changed

+103
-71
lines changed

‎build.sbt‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,8 @@ lazy val chipyard = {
175175

176176
// Optional modules discovered via initialized submodules (no env or manifest)
177177
val optionalModules: Seq[(String, ProjectReference)] = Seq(
178+
// Generators with Chipyard-facing glue compiled from their repos
179+
"cva6" -> cva6,
178180
"ara" -> ara,
179181
"saturn" -> saturn,
180182
"caliptra-aes-acc" -> caliptra_aes,

‎common.mk‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,6 @@ HELP_COMMANDS += \
7878
include $(base_dir)/generators/tracegen/tracegen.mk
7979
include $(base_dir)/tools/torture.mk
8080
# Optional generator make fragments should not fail build if absent
81-
-include $(base_dir)/generators/cva6/cva6.mk
8281
-include $(base_dir)/generators/ibex/ibex.mk
8382
-include $(base_dir)/generators/nvdla/nvdla.mk
8483
-include $(base_dir)/generators/radiance/radiance.mk

‎generators/chipyard/src/main/scala/config/CVA6Configs.scala‎

Lines changed: 0 additions & 19 deletions
This file was deleted.

‎generators/chipyard/src/main/scala/config/fragments/TileFragments.scala‎

Lines changed: 80 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ import freechips.rocketchip.subsystem._
88
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
99
import freechips.rocketchip.diplomacy._
1010

11-
import cva6.{CVA6TileAttachParams}
1211
import sodor.common.{SodorTileAttachParams}
1312
import ibex.{IbexTileAttachParams}
1413
import vexiiriscv.{VexiiRiscvTileAttachParams}
@@ -18,6 +17,43 @@ import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams}
1817
import tacit.{TacitEncoder, TacitBPParams}
1918
import shuttle.common.{ShuttleTileAttachParams}
2019

20+
// Static plugin discovery for optional generators via Java ServiceLoader.
21+
// Optional generators can implement TilePluginProvider and register using
22+
// META-INF/services without creating hard dependencies here.
23+
import scala.jdk.CollectionConverters._
24+
import org.reflections.Reflections
25+
import freechips.rocketchip.subsystem.HierarchicalElementPortParamsLike
26+
27+
trait TilePluginProvider {
28+
def tileTraceEnableInjectors: Seq[PartialFunction[Any, Any]] = Nil
29+
def tileTraceDisableInjectors: Seq[PartialFunction[Any, Any]] = Nil
30+
def tilePrefetchInjectors(make: (Int, HierarchicalElementPortParamsLike) => HierarchicalElementPortParamsLike): Seq[PartialFunction[Any, Any]] = Nil
31+
}
32+
33+
private object TilePlugins {
34+
private lazy val providers: Seq[TilePluginProvider] = {
35+
val reflections = new Reflections("chipyard")
36+
val subs = reflections.getSubTypesOf(classOf[TilePluginProvider]).asScala.toSeq.distinct
37+
subs.flatMap { cls =>
38+
try Some(cls.getDeclaredConstructor().newInstance())
39+
catch { case _: Throwable => None }
40+
}
41+
}
42+
43+
def traceEnableInjectors: Seq[PartialFunction[Any, Any]] =
44+
providers.flatMap(_.tileTraceEnableInjectors)
45+
def traceDisableInjectors: Seq[PartialFunction[Any, Any]] =
46+
providers.flatMap(_.tileTraceDisableInjectors)
47+
def prefetchInjectors(make: (Int, HierarchicalElementPortParamsLike) => HierarchicalElementPortParamsLike): Seq[PartialFunction[Any, Any]] =
48+
providers.flatMap(_.tilePrefetchInjectors(make))
49+
50+
def applyInjectors[A](tp: A, injectors: Seq[PartialFunction[Any, Any]]): A = {
51+
var acc: Any = tp
52+
injectors.foreach { pf => if (pf.isDefinedAt(acc)) acc = pf(acc) }
53+
acc.asInstanceOf[A]
54+
}
55+
}
56+
2157
class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
2258
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
2359
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -31,27 +67,29 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
3167
})
3268

3369
class WithTraceIO extends Config((site, here, up) => {
34-
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
35-
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
36-
core = tp.tileParams.core.copy(trace = true)))
37-
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
38-
core = tp.tileParams.core.copy(trace = true)))
39-
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
40-
trace = true))
41-
case other => other
70+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { tp =>
71+
val updated = tp match {
72+
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
73+
core = tp.tileParams.core.copy(trace = true)))
74+
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
75+
core = tp.tileParams.core.copy(trace = true)))
76+
case other => other
77+
}
78+
TilePlugins.applyInjectors(updated, TilePlugins.traceEnableInjectors)
4279
}
4380
case TracePortKey => Some(TracePortParams())
4481
})
4582

4683
class WithNoTraceIO extends Config((site, here, up) => {
47-
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
48-
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
49-
core = tp.tileParams.core.copy(trace = false)))
50-
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
51-
core = tp.tileParams.core.copy(trace = false)))
52-
case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
53-
trace = false))
54-
case other => other
84+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { tp =>
85+
val updated = tp match {
86+
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
87+
core = tp.tileParams.core.copy(trace = false)))
88+
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
89+
core = tp.tileParams.core.copy(trace = false)))
90+
case other => other
91+
}
92+
TilePlugins.applyInjectors(updated, TilePlugins.traceDisableInjectors)
5593
}
5694
case TracePortKey => None
5795
})
@@ -78,9 +116,9 @@ class WithTacitEncoder extends Config((site, here, up) => {
78116
nGroups = 1,
79117
xlen = tp.tileParams.core.xLen,
80118
iaddrWidth = tp.tileParams.core.xLen
81-
),
82-
bufferDepth = 16,
83-
coreStages = 5,
119+
),
120+
bufferDepth = 16,
121+
coreStages = 5,
84122
bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
85123
useArbiterMonitor = false
86124
)),
@@ -92,9 +130,9 @@ class WithTacitEncoder extends Config((site, here, up) => {
92130
nGroups = tp.tileParams.core.retireWidth,
93131
xlen = tp.tileParams.core.xLen,
94132
iaddrWidth = tp.tileParams.core.xLen
95-
),
96-
bufferDepth = 16,
97-
coreStages = 7,
133+
),
134+
bufferDepth = 16,
135+
coreStages = 7,
98136
bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
99137
useArbiterMonitor = false
100138
)),
@@ -144,21 +182,25 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
144182
})
145183

146184
class WithTilePrefetchers extends Config((site, here, up) => {
147-
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
148-
case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
149-
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
150-
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
151-
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
152-
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
153-
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
154-
case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
155-
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
156-
case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
157-
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
158-
case tp: VexiiRiscvTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
159-
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
160-
case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
161-
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
185+
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { tp =>
186+
val updated = tp match {
187+
case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
188+
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
189+
case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
190+
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
191+
case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
192+
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
193+
case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
194+
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
195+
case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
196+
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
197+
case tp: VexiiRiscvTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
198+
master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
199+
case other => other
200+
}
201+
val make = (tileId: Int, master: HierarchicalElementPortParamsLike) =>
202+
barf.TilePrefetchingMasterPortParams(tileId, master)
203+
TilePlugins.applyInjectors(updated, TilePlugins.prefetchInjectors(make))
162204
}
163205
})
164206

‎generators/cva6‎

‎scripts/init-submodules-no-riscv-tools-nolog.sh‎

Lines changed: 20 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ function usage
4040
echo " --compressacc Initialize the optional compressor accelerator submodule"
4141
echo " --mempress Initialize the optional mempress accelerator submodule"
4242
echo " --saturn Initialize the optional saturn vector-unit submodule"
43+
echo " --cva6 Initialize the optional CVA6 core submodule"
4344
echo ""
4445
}
4546

@@ -48,6 +49,7 @@ ENABLE_CALIPTRA=0
4849
ENABLE_COMPRESSACC=0
4950
ENABLE_MEMPRESS=0
5051
ENABLE_SATURN=0
52+
ENABLE_CVA6=0
5153

5254
while test $# -gt 0
5355
do
@@ -64,6 +66,7 @@ do
6466
ENABLE_COMPRESSACC=1
6567
ENABLE_MEMPRESS=1
6668
ENABLE_SATURN=1
69+
ENABLE_CVA6=1
6770
;;
6871
--ara)
6972
ENABLE_ARA=1
@@ -80,6 +83,9 @@ do
8083
--saturn)
8184
ENABLE_SATURN=1
8285
;;
86+
--cva6)
87+
ENABLE_CVA6=1
88+
;;
8389
*)
8490
echo "ERROR: bad argument $1"
8591
usage
@@ -163,18 +169,20 @@ cd "$RDIR"
163169
)
164170

165171
(
166-
# Non-recursive clone to exclude cva6 submods
167-
submodule_name="generators/cva6"
168-
git submodule update --init generators/cva6 || exit 1
169-
git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6 || exit 1
170-
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi || exit 1
171-
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi_riscv_atomics || exit 1
172-
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/common_cells || exit 1
173-
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/fpga-support || exit 1
174-
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/riscv-dbg || exit 1
175-
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/register_interface || exit 1
176-
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init --recursive src/fpu || exit 1
177-
172+
# Optional: non-recursive clone to exclude CVA6's heavy submodules unless requested
173+
if [[ "$ENABLE_CVA6" -eq 1 ]] ; then
174+
submodule_name="generators/cva6"
175+
git submodule update --init generators/cva6 || exit 1
176+
git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6 || exit 1
177+
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi || exit 1
178+
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi_riscv_atomics || exit 1
179+
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/common_cells || exit 1
180+
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/fpga-support || exit 1
181+
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/riscv-dbg || exit 1
182+
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/register_interface || exit 1
183+
git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init --recursive src/fpu || exit 1
184+
fi
185+
178186
# Non-recursive clone to exclude nvdla submods
179187
submodule_name="generators/nvdla"
180188
git submodule update --init generators/nvdla || exit 1

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