Test offchip-bus-switcher in CI

Author: jerryz123

.github/scripts/defaults.sh

@@ -56,7 +56,7 @@ mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_F
 mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
 mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
 mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
-mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
+mapping["chipyard-symmetric"]=" CONFIG=MultiSimMultiLinkSymmetricChipletRocketConfig"
 mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomV3Config verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"

.github/scripts/run-tests.sh

@@ -125,7 +125,8 @@ case $1 in
         ;;
     chipyard-symmetric)
         make -C $LOCAL_CHIPYARD_DIR/tests
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+offchip_sel=0"
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+offchip_sel=1"
         ;;
     chipyard-llcchiplet)
         make -C $LOCAL_CHIPYARD_DIR/tests

generators/chipyard/src/main/scala/config/ChipletConfigs.scala

@@ -84,7 +84,7 @@ class MultiLinkSymmetricChipletRocketConfig extends Config(
     replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
   ) ++
   new testchipip.soc.WithOffchipBus ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 // Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config