Merge branch 'ucb-bar-main' into graphics

Author: richardyrh

.github/scripts/defaults.sh

@@ -25,7 +25,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 
 # key value store to get the build groups
 declare -A grouping
-grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle chipyard-vexiiriscv"
+grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle chipyard-shuttle3 chipyard-vexiiriscv"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
 grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector chipyard-hlsacc" # chipyard-shuttleara - Add when Ara works again
 grouping["group-constellation"]="chipyard-constellation"
@@ -69,6 +69,7 @@ mapping["tracegen-boomv3"]=" CONFIG=BoomV3TraceGenConfig"
 mapping["tracegen-boomv4"]=" CONFIG=BoomV4TraceGenConfig"
 mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
 mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
+mapping["chipyard-shuttle3"]=" CONFIG=Shuttle3WideConfig"
 mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
 mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
 mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"

.github/scripts/run-tests.sh

@@ -50,7 +50,7 @@ case $1 in
         # Test cospike without checkpoint-restore
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1
         ;;
-    chipyard-boomv3|chipyard-boomv4|chipyard-shuttle|chipyard-spike)
+    chipyard-boomv3|chipyard-boomv4|chipyard-shuttle|chipyard-spike|chipyard-shuttle3)
         run_asm LOADMEM=1
         run_bmark LOADMEM=1
         ;;

.github/workflows/chipyard-run-tests.yml

@@ -512,6 +512,29 @@ jobs:
           group-key: "group-cores"
           project-key: "chipyard-shuttle"
 
+  chipyard-shuttle3-run-tests:
+    name: chipyard-shuttle3-run-tests
+    needs: prepare-chipyard-cores
+    runs-on: as4
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v4
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-cores"
+          project-key: "chipyard-shuttle3"
+
   chipyard-cva6-run-tests:
     name: chipyard-cva6-run-tests
     needs: prepare-chipyard-cores
@@ -1209,6 +1232,7 @@ jobs:
             chipyard-boomv3-run-tests,
             chipyard-boomv4-run-tests,
             chipyard-shuttle-run-tests,
+	    chipyard-shuttle3-run-tests,
             chipyard-cva6-run-tests,
             chipyard-ibex-run-tests,
             chipyard-vexiiriscv-run-tests,

fpga/src/main/scala/arty/HarnessBinders.scala

@@ -34,6 +34,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
     port.io.TCK := jtag_wire.TCK
     port.io.TMS := jtag_wire.TMS
     port.io.TDI := jtag_wire.TDI
+    port.io.reset.foreach(_ := th.referenceReset)
 
     val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
 

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -126,8 +126,12 @@ class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
 class WithArty100TJTAG extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
-    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
-    harnessIO <> port.io
+    val harnessIO = IO(new JTAGChipIO(false)).suggestName("jtag")
+    harnessIO.TDO := port.io.TDO
+    port.io.TCK := harnessIO.TCK
+    port.io.TDI := harnessIO.TDI
+    port.io.TMS := harnessIO.TMS
+    port.io.reset.foreach(_ := th.referenceReset)
 
     ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
     ath.sdc.addGroup(clocks = Seq("JTCK"))
@@ -138,6 +142,7 @@ class WithArty100TJTAG extends HarnessBinder({
       ("E2", IOPin(harnessIO.TDI)),
       ("D4", IOPin(harnessIO.TDO))
     )
+    
     packagePinsWithPackageIOs foreach { case (pin, io) => {
       ath.xdc.addPackagePin(io, pin)
       ath.xdc.addIOStandard(io, "LVCMOS33")

fpga/src/main/scala/vcu118/HarnessBinders.scala

@@ -43,6 +43,7 @@ class WithJTAG extends HarnessBinder({
     port.io.TCK := jtag_io.TCK
     port.io.TMS := jtag_io.TMS
     port.io.TDI := jtag_io.TDI
+    port.io.reset.foreach(_ := th.referenceReset)
     jtag_io.TDO.data := port.io.TDO
     jtag_io.TDO.driven := true.B
     // ignore srst_n

generators/chipyard/src/main/scala/config/ShuttleConfigs.scala

@@ -10,13 +10,25 @@ class ShuttleConfig extends Config(
   new shuttle.common.WithNShuttleCores ++                        // 1x dual-issue shuttle core
   new chipyard.config.AbstractConfig)
 
+class Shuttle3WideConfig extends Config(
+  new shuttle.common.WithNShuttleCores(retireWidth=3) ++         // 1x three-issue shuttle core
+  new chipyard.config.AbstractConfig)
+
+
 class ShuttleCosimConfig extends Config(
   new chipyard.harness.WithCospike ++                            // attach spike-cosim
   new chipyard.config.WithTraceIO ++                             // enable trace-io for cosim
   new shuttle.common.WithShuttleDebugROB ++                      // enable shuttle debug ROB for cosim
   new shuttle.common.WithNShuttleCores ++
   new chipyard.config.AbstractConfig)
 
+class Shuttle3WideCosimConfig extends Config(
+  new chipyard.harness.WithCospike ++                            // attach spike-cosim
+  new chipyard.config.WithTraceIO ++                             // enable trace-io for cosim
+  new shuttle.common.WithShuttleDebugROB ++                      // enable shuttle debug ROB for cosim
+  new shuttle.common.WithNShuttleCores(retireWidth=3) ++
+  new chipyard.config.AbstractConfig)
+
 class dmiShuttleCosimConfig extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.harness.WithCospike ++                            // attach spike-cosim

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -131,7 +131,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
     require(!debug.clockeddmi.isDefined)
     require(!debug.apb.isDefined)
     val (jtag_pad, jtagIOCells) = debug.systemjtag.map { j =>
-      val jtag_wire = Wire(new JTAGChipIO)
+      val jtag_wire = Wire(new JTAGChipIO(false))
       j.jtag.TCK := jtag_wire.TCK
       j.jtag.TMS := jtag_wire.TMS
       j.jtag.TDI := jtag_wire.TDI

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -187,6 +187,7 @@ class WithSimJTAGDebug extends HarnessBinder({
     port.io.TCK := jtag_wire.TCK
     port.io.TMS := jtag_wire.TMS
     port.io.TDI := jtag_wire.TDI
+    port.io.reset.foreach(_ := th.harnessBinderReset.asBool)
     val jtag = Module(new SimJTAG(tickDelay=3))
     jtag.connect(jtag_wire, th.harnessBinderClock, th.harnessBinderReset.asBool, ~(th.harnessBinderReset.asBool), dtm_success)
   }
@@ -205,6 +206,7 @@ class WithTiedOffJTAG extends HarnessBinder({
     port.io.TCK := true.B.asClock
     port.io.TMS := true.B
     port.io.TDI := true.B
+    port.io.reset.foreach(_ := true.B)
   }
 })
 

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -288,16 +288,18 @@ class WithExtInterruptIOCells extends OverrideIOBinder({
 })
 
 // Rocketchip's JTAGIO exposes the oe signal, which doesn't go off-chip
-class JTAGChipIO extends Bundle {
+class JTAGChipIO(hasReset: Boolean) extends Bundle {
   val TCK = Input(Clock())
   val TMS = Input(Bool())
   val TDI = Input(Bool())
   val TDO = Output(Bool())
+  val reset = Option.when(hasReset)(Input(Bool()))
 }
 
 // WARNING: Don't disable syncReset unless you are trying to
 // get around bugs in RTL simulators
-class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
+// If externalReset, exposes a reset in through JTAGChipIO, which is sync'd to TCK
+class WithDebugIOCells(syncReset: Boolean = true, externalReset: Boolean = true) extends OverrideLazyIOBinder({
   (system: HasPeripheryDebug) => {
     implicit val p = GetSystemParameters(system)
     val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
@@ -319,13 +321,6 @@ class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
           }
           // Tie off disableDebug
           d.disableDebug.foreach { d => d := false.B }
-          // Drive JTAG on-chip IOs
-          d.systemjtag.map { j =>
-            j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool)
-            j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
-            j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
-            j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
-          }
         }
         Debug.connectDebugClockAndReset(Some(debug), clockBundle.clock)
 
@@ -336,7 +331,15 @@ class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
         }
 
         val jtagTuple = debug.systemjtag.map { j =>
-          val jtag_wire = Wire(new JTAGChipIO)
+          val jtag_wire = Wire(new JTAGChipIO(externalReset))
+
+          // Drive JTAG on-chip IOs
+          val jReset = if (externalReset) jtag_wire.reset.get else clockBundle.reset.asBool
+          j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, jReset) else jReset)
+          j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
+          j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
+          j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
+
           j.jtag.TCK := jtag_wire.TCK
           j.jtag.TMS := jtag_wire.TMS
           j.jtag.TDI := jtag_wire.TDI