Merge pull request #1876 from ucb-bar/obus_switch

Support switchable C2C links through the OBUS

Author: jerryz123

.github/scripts/defaults.sh

@@ -60,7 +60,7 @@ mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_F
 mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
 mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
 mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
-mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
+mapping["chipyard-symmetric"]=" CONFIG=MultiSimMultiLinkSymmetricChipletRocketConfig"
 mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomV3Config verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"

.github/scripts/run-tests.sh

@@ -118,7 +118,8 @@ case $1 in
     chipyard-symmetric)
         build_tests
 
-        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+offchip_sel=0"
+	run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/symmetric.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+offchip_sel=1"
         ;;
     chipyard-llcchiplet)
         build_tests

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -19,6 +19,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
   with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register
   with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.soc.CanHaveSwitchableOffchipBus // Enables optional off-chip-bus with interface-switch
   with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
   with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
   with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -30,6 +30,7 @@ class AbstractConfig extends Config(
   new chipyard.harness.WithCustomBootPinPlusArg ++                 /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */
   new chipyard.harness.WithDriveChipIdPin ++                       /** drive chip id pin from harness binder, if chip id pin is present */
   new chipyard.harness.WithSimUARTToUARTTSI ++                     /** connect a SimUART to the UART-TSI port */
+  new chipyard.harness.WithOffchipBusSelPlusArg ++             /** drive offchip-bus-sel pin from plusArg */
   new chipyard.harness.WithClockFromHarness ++                     /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */
   new chipyard.harness.WithResetFromHarness ++                     /** reset controlled by harness */
   new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */
@@ -62,6 +63,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
   new chipyard.iobinders.WithGCDBusyPunchthrough ++
   new chipyard.iobinders.WithNMITiedOff ++
+  new chipyard.iobinders.WithOffchipBusSel ++
 
 
   // ================================================

generators/chipyard/src/main/scala/config/ChipletConfigs.scala

@@ -46,6 +46,57 @@ class MultiSimSymmetricChipletRocketConfig extends Config(
   new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
 )
 
+// Similar to the SymmetricChipletRocketConfig, but demonstrates a selectable c2c link
+// with two variants of the SerialTL interface
+class MultiLinkSymmetricChipletRocketConfig extends Config(
+  new testchipip.soc.WithChipIdPin ++                               // Add pin to identify chips
+  new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
+  new testchipip.serdes.WithSerialTL(Seq(
+    testchipip.serdes.SerialTLParams(                               // 0th serial-tl is chip-to-bringup-fpga
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // bringup serial-tl acts only as a client
+      phyParams = testchipip.serdes.DecoupledExternalSyncSerialPhyParams()   // bringup serial-tl is sync'd to external clock
+    ),
+    testchipip.serdes.SerialTLParams(                               // 1st serial-tl is narrow chip-to-chip
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // chip-to-chip serial-tl acts as a client
+      manager = Some(testchipip.serdes.SerialTLManagerParams(       // chip-to-chip serial-tl managers other chip's memory
+        memParams = Seq(testchipip.serdes.ManagerRAMParams(
+          address = 0,
+          size = 1L << 32,
+        )),
+        slaveWhere = OBUS
+      )),
+      phyParams = testchipip.serdes.CreditedSourceSyncSerialPhyParams(phitWidth=1) // narrow link
+    ),
+    testchipip.serdes.SerialTLParams(                               // 2nd serial-tl is wide chip-to-chip
+      client = Some(testchipip.serdes.SerialTLClientParams()),      // chip-to-chip serial-tl acts as a client
+      manager = Some(testchipip.serdes.SerialTLManagerParams(       // chip-to-chip serial-tl managers other chip's memory
+        memParams = Seq(testchipip.serdes.ManagerRAMParams(
+          address = 0,
+          size = 1L << 32,
+        )),
+        slaveWhere = OBUS
+      )),
+      phyParams = testchipip.serdes.CreditedSourceSyncSerialPhyParams(phitWidth=16) // wide link
+    ))
+  ) ++
+  new testchipip.soc.WithOffchipBusClient(SBUS,                     // obus provides path to other chip's memory
+    blockRange = Seq(AddressSet(0, (1L << 32) - 1)),                // The lower 4GB is mapped to this chip
+    replicationBase = Some(1L << 32)                                // The upper 4GB goes off-chip
+  ) ++
+  new testchipip.soc.WithOffchipBus ++
+  new freechips.rocketchip.rocket.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
+class MultiSimMultiLinkSymmetricChipletRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
+  new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=1) ++
+  new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=2, chip1portId=2) ++
+  new chipyard.harness.WithMultiChip(0, new MultiLinkSymmetricChipletRocketConfig) ++
+  new chipyard.harness.WithMultiChip(1, new MultiLinkSymmetricChipletRocketConfig)
+)
+
+
 // Core-only chiplet config, where the coherent memory is located on the LLC-chiplet
 class RocketCoreChipletConfig extends Config(
   new testchipip.serdes.WithSerialTL(Seq(

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -334,3 +334,10 @@ class WithResetFromHarness extends HarnessBinder({
   }
 })
 
+class WithOffchipBusSelPlusArg extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: OffchipSelPort, chipId: Int) => {
+    val pin = PlusArg("offchip_sel", width=port.io.getWidth)
+    port.io := pin
+  }
+})
+

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -32,7 +32,7 @@ import chipyard.iocell._
 import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
 import testchipip.spi.{SPIChipIO}
 import testchipip.boot.{CanHavePeripheryCustomBootPin}
-import testchipip.soc.{CanHavePeripheryChipIdPin}
+import testchipip.soc.{CanHavePeripheryChipIdPin, CanHaveSwitchableOffchipBus}
 import testchipip.util.{ClockedIO}
 import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
 import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
@@ -567,3 +567,13 @@ class WithGCDBusyPunchthrough extends OverrideIOBinder({
     (Seq(GCDBusyPort(() => io_gcd_busy)), Nil)
   }.getOrElse((Nil, Nil))
 })
+
+class WithOffchipBusSel extends OverrideIOBinder({
+  (system: CanHaveSwitchableOffchipBus) => {
+    system.io_obus_sel.getWrappedValue.map { sel =>
+      val sys = system.asInstanceOf[BaseSubsystem]
+      val (port, cells) = IOCell.generateIOFromSignal(sel, "obus_sel", sys.p(IOCellKey))
+      (Seq(OffchipSelPort(() => port)), cells)
+    }.getOrElse(Nil, Nil)
+  }
+})

generators/chipyard/src/main/scala/iobinders/Ports.scala

@@ -111,3 +111,7 @@ case class TLMemPort       (val getIO: () => HeterogeneousBag[TLBundle])
 
 case class GCDBusyPort     (val getIO: () => Bool)
     extends Port[Bool]
+
+case class OffchipSelPort  (val getIO: () => UInt)
+    extends Port[UInt]
+