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ADD: config framents and example config for tacit
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generators/chipyard/src/main/scala/config/RocketConfigs.scala

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@@ -115,3 +115,10 @@ class SV48RocketConfig extends Config(
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new freechips.rocketchip.rocket.WithSV48 ++
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new freechips.rocketchip.rocket.WithNHugeCores(1) ++
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new chipyard.config.AbstractConfig)
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class LTraceEncoderRocketConfig extends Config(
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new chipyard.config.WithLTraceEncoder ++
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new chipyard.config.WithNPerfCounters(29) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.rocket.WithNHugeCores(1) ++
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new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

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@@ -14,6 +14,8 @@ import vexiiriscv.{VexiiRiscvTileAttachParams}
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import testchipip.cosim.{TracePortKey, TracePortParams}
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import barf.{TilePrefetchingMasterPortParams}
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import freechips.rocketchip.util.{TraceEncoderParams, TraceCoreParams}
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class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -64,6 +66,25 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
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}
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})
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class WithLTraceEncoder extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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ltrace = Some(new TraceEncoderParams(
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coreParams = new TraceCoreParams(
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nGroups = 1,
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iretireWidth = 1,
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xlen = tp.tileParams.core.xLen,
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iaddrWidth = tp.tileParams.core.xLen
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),
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bufferDepth = 16,
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encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
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sinkDMABaseAddr = 0x3010000 + tp.tileParams.tileId * 0x1000,
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useSinkPrint = true,
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useSinkDMA = true
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))))
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}
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})
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class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
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case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
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case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(

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