@@ -14,6 +14,8 @@ import vexiiriscv.{VexiiRiscvTileAttachParams}
1414import testchipip .cosim .{TracePortKey , TracePortParams }
1515import barf .{TilePrefetchingMasterPortParams }
1616
17+ import freechips .rocketchip .util .{TraceEncoderParams , TraceCoreParams }
18+
1719class WithL2TLBs (entries : Int ) extends Config ((site, here, up) => {
1820 case TilesLocated (InSubsystem ) => up(TilesLocated (InSubsystem ), site) map {
1921 case tp : RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -64,6 +66,25 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
6466 }
6567})
6668
69+ class WithLTraceEncoder extends Config ((site, here, up) => {
70+ case TilesLocated (InSubsystem ) => up(TilesLocated (InSubsystem ), site) map {
71+ case tp : RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
72+ ltrace = Some (new TraceEncoderParams (
73+ coreParams = new TraceCoreParams (
74+ nGroups = 1 ,
75+ iretireWidth = 1 ,
76+ xlen = tp.tileParams.core.xLen,
77+ iaddrWidth = tp.tileParams.core.xLen
78+ ),
79+ bufferDepth = 16 ,
80+ encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000 ,
81+ sinkDMABaseAddr = 0x3010000 + tp.tileParams.tileId * 0x1000 ,
82+ useSinkPrint = true ,
83+ useSinkDMA = true
84+ ))))
85+ }
86+ })
87+
6788class WithNPMPs (n : Int = 8 ) extends Config ((site, here, up) => {
6889 case TilesLocated (InSubsystem ) => up(TilesLocated (InSubsystem ), site) map {
6990 case tp : RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
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