Merge pull request #1249 from ucb-bar/misc-fixes

Misc release cleanup

Author: abejgonzalez

.gitattributes

@@ -1,2 +1,2 @@
-conda-requirements-esp-tools-linux-64.conda-lock.yml linguist-generated=true
-conda-requirements-riscv-tools-linux-64.conda-lock.yml linguist-generated=true
+conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml linguist-generated=true
+conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml linguist-generated=true

.github/actions/create-conda-env/action.yml

@@ -16,8 +16,8 @@ runs:
         else
           echo "Creating a conda environment for each toolchain with the toolchain installed"
           conda activate base
-          conda-lock install -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools ./conda-requirements-riscv-tools-linux-64.conda-lock.yml
-          conda-lock install -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools ./conda-requirements-esp-tools-linux-64.conda-lock.yml
+          conda-lock install -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools ./conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+          conda-lock install -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools ./conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
           conda deactivate
 
           if [[ "${{ inputs.install-collateral }}" == 'true' ]]; then

.gitignore

@@ -13,12 +13,8 @@ target
 .idea
 .DS_Store
 env.sh
-riscv-tools-install
-esp-tools-install
 tags
 *~
-env-riscv-tools.sh
-env-esp-tools.sh
 .bsp/
 .conda-env/
-.#*
+.#*

build-setup.sh

@@ -62,12 +62,13 @@ done
 
 if [ "$SKIP_CONDA" = false ]; then
     # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
-    LOCKFILE=$RDIR/conda-requirements-$TOOLCHAIN-linux-64.conda-lock.yml
-    YAMLFILE=$RDIR/conda-requirements-$TOOLCHAIN.yaml
+    CONDA_REQS=$RDIR/conda-reqs
+    CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs
+    LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN-linux-64.conda-lock.yml
 
     if [ "$USE_PINNED_DEPS" = false ]; then
         # auto-gen the lockfile
-        conda-lock -f $YAMLFILE -p linux-64 --lockfile $LOCKFILE
+        conda-lock -f $CONDA_REQS/chipyard.yaml -f $CONDA_REQS/$TOOLCHAIN.yaml --lockfile $LOCKFILE
     fi
 
     # use conda-lock to create env

common.mk

@@ -4,7 +4,7 @@
 SHELL=/bin/bash
 
 ifndef RISCV
-$(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file)
+$(error RISCV is unset. Did you source the Chipyard auto-generated env file (which activates the default conda environment)?)
 else
 $(info Running with RISCV=$(RISCV))
 endif
@@ -101,12 +101,8 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 #########################################################################################
 # create firrtl file rule and variables
 #########################################################################################
-.INTERMEDIATE: generator_temp
-$(FIRRTL_FILE) $(ANNO_FILE): generator_temp
-	@echo "" > /dev/null
-
 # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
-generator_temp: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
+$(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
 	mkdir -p $(build_dir)
 	$(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
 		--target-dir $(build_dir) \
@@ -128,12 +124,7 @@ TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_bla
 HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes)
 
 # DOC include start: FirrtlCompiler
-# NOTE: These *_temp intermediate targets will get removed in favor of make 4.3 grouped targets (&: operator)
-.INTERMEDIATE: firrtl_temp
-$(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp
-	@echo "" > /dev/null
-
-firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
+$(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
 	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,\
 		--allow-unrecognized-annotations \
 		--output-file $(TOP_FILE) \
@@ -158,19 +149,11 @@ firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 MACROCOMPILER_MODE ?= --mode synflops
-.INTERMEDIATE: top_macro_temp
-$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): top_macro_temp
-	@echo "" > /dev/null
-
-top_macro_temp: $(TOP_SMEMS_CONF)
+$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF)
 	$(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE))
 
 HARNESS_MACROCOMPILER_MODE = --mode synflops
-.INTERMEDIATE: harness_macro_temp
-$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): harness_macro_temp
-	@echo "" > /dev/null
-
-harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp
+$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEMS_FILE)
 	$(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE))
 
 ########################################################################################

conda-requirements-esp-tools.yaml conda-reqs/chipyard.yamlconda-requirements-esp-tools.yaml renamed to conda-reqs/chipyard.yaml

@@ -3,6 +3,9 @@ channels:
     - conda-forge
     - nodefaults
 
+platforms:
+    - linux-64
+
 dependencies:
     # https://conda-forge.org/feedstock-outputs/
     #   filterable list of all conda-forge packages
@@ -26,7 +29,6 @@ dependencies:
     - binutils
 
     - dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo
-    - esp-tools # from ucb-bar channel - https://github.com/ucb-bar/esp-tools-feedstock
 
     # firemarshal deps
     - python>=3.8