Modularize out cores

Author: jerryz123

build.sbt

@@ -160,9 +160,9 @@ lazy val chipyard = {
     .dependsOn(
       testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
       dsptools, rocket_dsp_utils,
-      radiance, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
+      radiance, gemmini, icenet, tracegen, nvdla, fft_generator,
       constellation, barf, shuttle, rerocc,
-      firrtl2_bridge, vexiiriscv, tacit
+      firrtl2_bridge, tacit
     )
     .settings(libraryDependencies ++= rocketLibDeps.value)
     .settings(
@@ -175,6 +175,11 @@ lazy val chipyard = {
 
   // Optional modules discovered via initialized submodules (no env or manifest)
   val optionalModules: Seq[(String, ProjectReference)] = Seq(
+    // Generators with Chipyard-facing glue compiled from their repos
+    "cva6" -> cva6,
+    "ibex" -> ibex,
+    "vexiiriscv" -> vexiiriscv,
+    "riscv-sodor" -> sodor,
     "ara" -> ara,
     "saturn" -> saturn,
     "caliptra-aes-acc" -> caliptra_aes,

common.mk

@@ -78,7 +78,6 @@ HELP_COMMANDS += \
 include $(base_dir)/generators/tracegen/tracegen.mk
 include $(base_dir)/tools/torture.mk
 # Optional generator make fragments should not fail build if absent
--include $(base_dir)/generators/cva6/cva6.mk
 -include $(base_dir)/generators/ibex/ibex.mk
 -include $(base_dir)/generators/nvdla/nvdla.mk
 -include $(base_dir)/generators/radiance/radiance.mk

docs/Chipyard-Basics/Configs-Parameters-Mixins.rst

@@ -123,3 +123,11 @@ Another description of traits/mixins and config fragments is given in :ref:`Cust
 Additionally, a brief explanation of some of these topics (with slightly different naming) is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY.
 
 .. Note:: Chipyard uses the name "config fragments" over "config mixins" to avoid confusion between a mixin applying to a config or to the system ``Top`` (even though both are technically Scala mixins).
+
+Optional Generator Injectors
+----------------------------
+
+Some generic Chipyard config fragments (for example, trace toggles and tile prefetch settings) are designed to affect optional generators without hard dependencies. Chipyard discovers generator-provided injectors at elaboration time and applies them, allowing fragments like ``WithTraceIO`` and ``WithTilePrefetchers`` to work across different tiles.
+
+- Generators that want to participate implement ``chipyard.config.TilePluginProvider`` under their ``generators/<name>/chipyard`` sources. Chipyard discovers implementations via classpath scanning and applies the provided injectors.
+- This keeps the core fragments generic, while enabling per-generator behavior (e.g., mapping a prefetch intent to the correct port parameters for that tile).

docs/Chipyard-Basics/Initial-Repo-Setup.rst

@@ -97,6 +97,8 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di
 
 .. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc).
 
+.. Note for power users: Chipyard includes internal scripts that can selectively initialize generator submodules. The default ``./build-setup.sh`` initializes all standard generator submodules and is the recommended path.
+
 .. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
 
 By running the following command you should see an environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``.

docs/Generators/CVA6.rst

@@ -2,13 +2,19 @@ CVA6 Core
 ====================================
 
 `CVA6 <https://github.com/openhwgroup/cva6>`__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
-The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
+The `CVA6 core` is wrapped in a `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
 The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
 
 .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
 
 While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters).
 
+Configuration classes and Chipyard glue for CVA6 live under ``generators/cva6/chipyard`` and are compiled directly from the CVA6 repository sources. After running the standard setup (``./build-setup.sh``), you can build a CVA6 config like ``CVA6Config`` with the normal flow:
+
+::
+
+  cd sims/vcs && make CONFIG=CVA6Config
+
 .. Warning::  This target does not support Verilator simulation at this time. Please use VCS.
 
 For more information, please refer to the `GitHub repository <https://github.com/openhwgroup/cva6>`__.

docs/Generators/Ibex.rst

@@ -9,6 +9,12 @@ The core exposes a custom memory interface, interrupt ports, and other misc. por
 
 .. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80.
 
-While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
-
+While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
+
 For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.
+
+Configuration classes and Chipyard glue for Ibex live under ``generators/ibex/chipyard`` and are compiled directly from the Ibex repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
+
+::
+
+  cd sims/vcs && make CONFIG=IbexConfig

docs/Generators/Sodor.rst

@@ -15,3 +15,9 @@ The five available cores and their corresponding generator configuration are:
 * "bus"-based micro-coded implementation - ``SodorUCodeConfig``
 
 For more information, please refer to the `GitHub repository <https://github.com/ucb-bar/riscv-sodor>`__.
+
+Configuration classes and Chipyard glue for Sodor live under ``generators/riscv-sodor/chipyard`` and are compiled directly from the Sodor repository sources. After running the standard setup (``./build-setup.sh``), build a config (e.g., 3-stage) with:
+
+::
+
+  cd sims/vcs && make CONFIG=Sodor3StageConfig

docs/Generators/VexiiRiscv.rst

@@ -7,3 +7,8 @@ VexiiRiscv implements cache-coherent TileLink L1 data caches and is integrated a
 The example VexiiRiscv config is ``VexiiRiscvConfig``.
 When building this Config, Chipyard will call VexiiRiscv's SpinalHDL RTL generator to generate the core's SystemVerilog, before integrating it as a Chisel blackbox.
 
+Configuration classes and Chipyard glue for VexiiRiscv live under ``generators/vexiiriscv/chipyard`` and are compiled directly from the VexiiRiscv repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
+
+::
+
+  cd sims/vcs && make CONFIG=VexiiRiscvConfig