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CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep ^-
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CHECK_SUBMODULES_COMMAND = echo "Checking required submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep '^-.*' | grep -vE "(ara|caliptra|compress|mempress|saturn)"
Copy file name to clipboardExpand all lines: docs/Generators/Ara.rst
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@@ -3,7 +3,7 @@ Ara
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`Ara <https://github.com/pulp-platform/ara>`__ is a RISC-V vector unit developed by the PULP project.
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The Ara vector unit supports integration with either the Rocket or Shuttle in-order cores, following a similar methodology as used in the original Ara+CVA6 system.
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Example Ara configurations are listed in ``generators/chipyard/src/main/scala/config/AraConfigs.scala``.
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Example Ara configurations are provided by the Ara repository and compiled directly from ``generators/ara/chipyard/`` when the Ara submodule is initialized.
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.. Warning:: Ara only supports a partial subset of the full V-extension. Notably, we do not support virtual memory or precise traps with Ara.
Copy file name to clipboardExpand all lines: docs/Generators/Saturn.rst
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@@ -5,7 +5,7 @@ Saturn is a parameterized RISC-V Vector Unit generator currently supporting inte
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Saturn implements a compact short-vector-length vector microarchitecture suitable for deployment in a DSP-optimized core or area-efficient general-purpose core.
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More documentation on Saturn will be released in the future.
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A partial listing of supported Saturn configurations is in ``generators/chipyard/src/main/scala/config/SaturnConfigs.scala``.
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A partial listing of supported Saturn configurations is maintained in the Saturn repository and compiled directly from ``generators/saturn/chipyard/`` when the Saturn submodule is initialized.
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For now, the recommended Saturn configuration is ``GENV256D128ShuttleConfig``, which builds a dual-issue core with 256-bit VLEN, 128-bit wide SIMD datapath, and separate floating-point and integer vector issue units.
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* ``Zve64d`` support for vector FP32 and FP64
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* Configurable vector length, from ``Zvl64b`` up (tested to ``Zvl4096b``)
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* Configurable datapath width, from 64b up (tested to 512b)
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