fix configs, scripts, makefile, and other stuff for merge

richardyrh · richardyrh · commit baef8218594c · 2025-02-07T19:00:48.000-08:00
diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
@@ -46,7 +46,7 @@ search () {
 }
 
 
-submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv")
+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv" "radiance")
 dir="generators"
 branches=("master" "main" "dev")
 search
diff --git a/common.mk b/common.mk
@@ -17,6 +17,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_SOURCES         = additional simulation sources needed for simulator" \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
 "   EXTRA_SIM_OUT_NAME        = additional suffix appended to the simulation .out log filename" \
+"   EXTRA_SIM_PREPROC_DEFINES = additional defines passed to the simulator" \
 "   ENABLE_YOSYS_FLOW         = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \
 "   MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \
diff --git a/conda-reqs/chipyard-extended.yaml b/conda-reqs/chipyard-extended.yaml
@@ -46,8 +46,6 @@ dependencies:
     - findutils
     - lzop
 
-    # dpi module
-    - rust
 
     - bash-completion
     - ca-certificates
diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
@@ -15,236 +15,6 @@ class MemtraceCoreConfig extends Config(
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++
   new chipyard.config.WithSystemBusWidth(16 * 8) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
+  new chipyard.NoCoresConfig
   )
 
-
-/////////////////////////////////////////////////
-/// Various Configs for perf testing (feel free to delete them later)
-/////////////////////////////////////////////////
-
-class MemtraceCoreNV64B2IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(64) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV128B2IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV256B2IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(256) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV512B2IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=2) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=2) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(512) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV64B8IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(64) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV128B8IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV256B8IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(256) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV512B8IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=8) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=8) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(512) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV64B16IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(64) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV128B16IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV256B16IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(256) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV512B16IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=16) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=16) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(512) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV64B32IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(64) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV128B32IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV256B32IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(256) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
-
-class MemtraceCoreNV512B32IdConfig extends Config(
-  new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds=32) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes=32, nSrcIds=32) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(512) ++
-  // Small Rocket core that does nothing
-  new radiance.subsystem.WithNCustomSmallRocketCores(1) ++
-  new chipyard.config.AbstractConfig
-  )
diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
@@ -8,16 +8,6 @@ import freechips.rocketchip.subsystem._
 import org.chipsalliance.cde.config.Config
 import radiance.subsystem.RadianceGemminiDataType
 
-class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => {
-  case BootROMLocated(x) => up(BootROMLocated(x))
-    .map(_.copy(
-      address = address,
-      size = size,
-      hang = hang,
-      contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv32.img"
-    ))
-})
-
 // ----------------
 // Radiance Configs
 // ----------------
@@ -38,7 +28,6 @@ class RadianceBaseConfig extends Config(
   new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
   new WithExtMemSize(BigInt("80000000", 16)) ++
   new WithRadBootROM() ++
-  new chipyard.iobinders.WithCeasePunchThrough ++
   new radiance.subsystem.WithRadianceSimParams(true) ++
   new WithCacheBlockBytes(64) ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
@@ -158,16 +147,11 @@ class RadianceNoCoalConfig extends Config(
 class RadianceEmulatorConfig extends Config(
   new radiance.subsystem.WithEmulatorCores(1, useVxCache = false) ++
   new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 4) ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new chipyard.harness.WithCeaseSuccess ++
-  new chipyard.iobinders.WithCeasePunchThrough ++
   new AbstractConfig)
 
 class RadianceFuzzerConfig extends Config(
   new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++
   new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++
   new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 2) ++
   new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new chipyard.harness.WithCeaseSuccess ++
-  new chipyard.iobinders.WithCeasePunchThrough ++
   new AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -162,6 +162,16 @@ class WithNoBootROM extends Config((site, here, up) => {
   case BootROMLocated(_) => None
 })
 
+class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => {
+  case BootROMLocated(x) => up(BootROMLocated(x))
+    .map(_.copy(
+      address = address,
+      size = size,
+      hang = hang,
+      contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv32.img"
+    ))
+})
+
 class WithNoBusErrorDevices extends Config((site, here, up) => {
   case SystemBusKey => up(SystemBusKey).copy(errorDevice = None)
   case ControlBusKey => up(ControlBusKey).copy(errorDevice = None)
diff --git a/toolchains/riscv-tools/riscv-tools-feedstock b/toolchains/riscv-tools/riscv-tools-feedstock
@@ -1 +1 @@
-Subproject commit 917b56ef1a78871be22283ecdb01658ac11cbe61
+Subproject commit 56c29e01ba3e705c563edd1271a387119bddb5a5

Original file line number	Diff line number	Diff line change
`@@ -46,7 +46,7 @@ search () {`
`46`	`46`	`}`
`47`	`47`
`48`	`48`
`49`		`-submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv")`
	`49`	`+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv" "radiance")`
`50`	`50`	`dir="generators"`
`51`	`51`	`branches=("master" "main" "dev")`
`52`	`52`	`search`