Update preproc defines doc

Author: hansungk

common.mk

@@ -17,7 +17,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_SOURCES         = additional simulation sources needed for simulator" \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
 "   EXTRA_SIM_OUT_NAME        = additional suffix appended to the simulation .out log filename" \
-"   EXTRA_SIM_PREPROC_DEFINES = additional defines passed to the simulator" \
+"   EXTRA_SIM_PREPROC_DEFINES = additional Verilog preprocessor defines passed to the simulator" \
 "   ENABLE_YOSYS_FLOW         = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \
 "   MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \