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jerryz123jerryz123
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Merge pull request #2136 from doihead/intel-fpgas
Add support for Intel/Altera FPGAs + Trenz Datastorm board
2 parents 146f62f + 58b4ea6 commit d4ebf93

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5 files changed

+296
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lines changed

5 files changed

+296
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‎fpga/Makefile

+26
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,19 @@ ifeq ($(SUB_PROJECT),arty100t)
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BOARD ?= arty_a7_100
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FPGA_BRAND ?= xilinx
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endif
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ifeq ($(SUB_PROJECT),datastorm)
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SBT_PROJECT ?= chipyard_fpga
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MODEL ?= DatastormHarness
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VLOG_MODEL ?= DatastormHarness
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MODEL_PACKAGE ?= chipyard.fpga.datastorm
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CONFIG ?= RocketDatastormConfig
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CONFIG_PACKAGE ?= chipyard.fpga.datastorm
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GENERATOR_PACKAGE ?= chipyard
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TB ?= none # unused
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TOP ?= ChipTop
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BOARD ?= trenz_datastorm
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FPGA_BRAND ?= altera
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endif
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90103
export USE_CHISEL6=1
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@@ -133,9 +146,11 @@ all_vsrcs := \
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# combine all sources into single .f
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synth_list_f := $(build_dir)/$(long_name).vsrcs.f
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$(synth_list_f): $(sim_common_files) $(all_vsrcs)
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rm -f $@
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$(foreach file,$(all_vsrcs),echo "$(file)" >> $@;)
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cat $(sim_common_files) >> $@
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ifeq ($(FPGA_BRAND),xilinx)
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BIT_FILE := $(build_dir)/obj/$(MODEL).bit
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$(BIT_FILE): $(synth_list_f)
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cd $(build_dir); vivado \
@@ -146,6 +161,17 @@ $(BIT_FILE): $(synth_list_f)
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-F "$(synth_list_f)" \
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-board "$(BOARD)" \
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-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')"
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endif
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ifeq ($(FPGA_BRAND),altera)
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BIT_FILE := $(build_dir)/output_files/$(MODEL).qsf
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$(BIT_FILE): $(synth_list_f)
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cd $(build_dir); quartus_sh \
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-t $(fpga_common_script_dir)/quartus.tcl \
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"$(MODEL)" \
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"$(BOARD)" \
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"$(long_name)" \
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"$(shell find '$(build_dir)' -name '*.quartus.tcl')"
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endif
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150176
.PHONY: bitstream
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bitstream: $(BIT_FILE)

‎fpga/fpga-shells

Submodule fpga-shells updated 20 files

‎fpga/src/main/scala/datastorm/Configs.scala

+61
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
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// See LICENSE for license details.
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package chipyard.fpga.datastorm
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import org.chipsalliance.diplomacy._
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import org.chipsalliance.diplomacy.lazymodule._
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.uart._
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import sifive.fpgashells.shell.{DesignKey}
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import testchipip.serdes.{SerialTLKey}
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import chipyard.{BuildSystem}
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import testchipip.soc.WithNoScratchpads
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import sifive.blocks.devices.spi.SPIProtocol.width
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import chipyard.iobinders.WithGPIOPunchthrough
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// don't use FPGAShell's DesignKey
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class WithNoDesignKey extends Config((site, here, up) => {
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case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
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})
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class WithDatastormTweaks(freqMHz: Double = 40) extends Config(
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new WithDatastormPMODUART ++
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new WithDatastormUARTTSI ++
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new WithDatastormDDRTL ++
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new WithDatastormJTAG ++
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new WithNoDesignKey ++
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new testchipip.tsi.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++
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new chipyard.harness.WithSerialTLTiedOff ++
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new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
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new chipyard.config.WithUniformBusFrequencies(freqMHz) ++
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new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
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new chipyard.clocking.WithPassthroughClockGenerator ++
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new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
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new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(1) << 30) ++ // 1GB on Datastorm
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new freechips.rocketchip.subsystem.WithoutTLMonitors)
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class RocketDatastormConfig extends Config(
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new WithDatastormTweaks ++
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new WithNoScratchpads ++
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new testchipip.serdes.WithNoSerialTL ++
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new chipyard.config.WithBroadcastManager ++ // no l2
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new freechips.rocketchip.rocket.WithNBigCores(1) ++ // Use bigrocket instead of huge due to space constraints
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new chipyard.config.AbstractConfig)
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class NoCoresDatastormConfig extends Config(
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new WithDatastormTweaks ++
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new chipyard.config.WithBroadcastManager ++ // no l2
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new chipyard.NoCoresConfig)
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class BringupDatastormConfig extends Config(
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new WithDatastormSerialTLToFMC ++
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new WithDatastormTweaks ++
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new testchipip.serdes.WithSerialTLPHYParams(testchipip.serdes.InternalSyncSerialPhyParams(freqMHz=40)) ++
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new chipyard.ChipBringupHostConfig)

‎fpga/src/main/scala/datastorm/Harness.scala

+83
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@@ -0,0 +1,83 @@
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package chipyard.fpga.datastorm
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.diplomacy._
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import org.chipsalliance.cde.config.{Parameters}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.prci._
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import freechips.rocketchip.subsystem.{SystemBusKey}
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import sifive.fpgashells.shell.altera._
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import sifive.fpgashells.shell._
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import sifive.fpgashells.clocks._
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import sifive.blocks.devices.uart._
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import chipyard._
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import chipyard.harness._
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class DatastormHarness(override implicit val p: Parameters) extends DatastormShell {
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def dp = designParameters
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val clockOverlay = dp(ClockInputOverlayKey).map(_.place(ClockInputDesignInput())).head
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val harnessSysPLL = dp(PLLFactoryKey)
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val harnessSysPLLNode = harnessSysPLL()
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val dutFreqMHz = (dp(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toInt
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val dutClock = ClockSinkNode(freqMHz = dutFreqMHz)
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println(s"Datastorm FPGA Base Clock Freq: ${dutFreqMHz} MHz")
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val dutWrangler = LazyModule(new ResetWrangler())
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val dutGroup = ClockGroup()
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dutClock := dutWrangler.node := dutGroup := harnessSysPLLNode
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harnessSysPLLNode := clockOverlay.overlayOutput.node
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val ddrOverlay = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtTLMem).get.master.base, dutWrangler.node, harnessSysPLLNode)).asInstanceOf[DDRDatastormPlacedOverlay]
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val ddrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
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name = "chip_ddr",
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sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
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)))))
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val ddrBlockDuringReset = LazyModule(new TLBlockDuringReset(4))
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ddrOverlay.overlayOutput.ddr := ddrBlockDuringReset.node := ddrClient
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val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput()))
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val all_leds = ledOverlays.map(_.overlayOutput.led)
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override lazy val module = new HarnessLikeImpl
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class HarnessLikeImpl extends Impl with HasHarnessInstantiators {
49+
clockOverlay.overlayOutput.node.out(0)._1.reset := ~resetPin
50+
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val clk_50mhz = clockOverlay.overlayOutput.node.out.head._1.clock
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// Blink the status LEDs for sanity
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withClockAndReset(clk_50mhz, dutClock.in.head._1.reset) {
55+
val period = (BigInt(50) << 20)
56+
val counter = RegInit(0.U(log2Ceil(period).W))
57+
val on = RegInit(false.B)
58+
all_leds(0) := on
59+
counter := Mux(counter === (period-1).U, 0.U, counter + 1.U)
60+
when (counter === 0.U) {
61+
on := !on
62+
}
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}
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65+
harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
66+
67+
def referenceClockFreqMHz = dutFreqMHz
68+
def referenceClock = dutClock.in.head._1.clock
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def referenceReset = dutClock.in.head._1.reset
70+
def success = { require(false, "Unused"); false.B }
71+
72+
childClock := harnessBinderClock
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childReset := harnessBinderReset
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75+
ddrOverlay.mig.module.clock := harnessBinderClock
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ddrOverlay.mig.module.reset := harnessBinderReset
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ddrBlockDuringReset.module.clock := harnessBinderClock
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ddrBlockDuringReset.module.reset := harnessBinderReset.asBool || !ddrOverlay.mig.module.io.port.mem_status_local_cal_success
79+
80+
all_leds(1) := ddrOverlay.mig.module.io.port.mem_status_local_cal_success
81+
instantiateChipTops()
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}
83+
}

‎fpga/src/main/scala/datastorm/HarnessBinders.scala

+125
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@@ -0,0 +1,125 @@
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package chipyard.fpga.datastorm
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import chisel3._
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import freechips.rocketchip.jtag.{JTAGIO}
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import freechips.rocketchip.subsystem.{PeripheryBusKey}
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import freechips.rocketchip.tilelink.{TLBundle}
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import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
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import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
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import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
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import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
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import sifive.blocks.devices.pinctrl.{BasePin}
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import sifive.fpgashells.shell._
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import sifive.fpgashells.ip.altera._
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import sifive.fpgashells.shell.altera._
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import sifive.fpgashells.clocks._
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import chipyard._
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import chipyard.harness._
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import chipyard.iobinders._
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import testchipip.serdes._
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class WithDatastormDDRTL extends HarnessBinder({
23+
case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
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val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[DatastormHarness]
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val bundles = ath.ddrClient.out.map(_._1)
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val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
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bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
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ddrClientBundle <> port.io
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}
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})
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class WithDatastormSerialTLToFMC extends HarnessBinder({
33+
case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) => {
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val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[DatastormHarness]
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val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
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harnessIO <> port.io
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harnessIO match {
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case io: DecoupledPhitIO => {
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val clkIO = io match {
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case io: InternalSyncPhitIO => IOPin(io.clock_out)
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case io: ExternalSyncPhitIO => IOPin(io.clock_in)
43+
}
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val packagePinsWithPackageIOs = Seq(
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("PIN_C13", clkIO),
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("PIN_J12", IOPin(io.out.valid)),
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("PIN_K12", IOPin(io.out.ready)),
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("PIN_H12", IOPin(io.in.valid)),
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("PIN_H13", IOPin(io.in.ready)),
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("PIN_E9", IOPin(io.out.bits.phit, 0)),
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("PIN_D9", IOPin(io.out.bits.phit, 1)),
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("PIN_H14", IOPin(io.out.bits.phit, 2)),
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("PIN_G13", IOPin(io.out.bits.phit, 3)),
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("PIN_C12", IOPin(io.in.bits.phit, 0)),
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("PIN_B11", IOPin(io.in.bits.phit, 1)),
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("PIN_E8", IOPin(io.in.bits.phit, 2)),
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("PIN_D7", IOPin(io.in.bits.phit, 3))
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)
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packagePinsWithPackageIOs foreach { case (pin, io) => {
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ath.io_tcl.addPackagePin(io, pin)
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ath.io_tcl.addIOStandard(io, "1.5 V")
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}}
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ath.sdc.addClock("ser_tl_clock", clkIO, 50)
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ath.sdc.addGroup(clocks = Seq("ser_tl_clock"))
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}
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}
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}
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})
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class WithDatastormUARTTSI extends HarnessBinder({
72+
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
73+
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[DatastormHarness]
74+
val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
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harnessIO <> port.io.uart
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val packagePinsWithPackageIOs = Seq(
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("PIN_AG10" , IOPin(harnessIO.rxd)),
78+
("PIN_AH9", IOPin(harnessIO.txd)))
79+
packagePinsWithPackageIOs foreach { case (pin, io) => {
80+
ath.io_tcl.addPackagePin(io, pin)
81+
ath.io_tcl.addIOStandard(io, "1.5 V")
82+
} }
83+
}
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})
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86+
// Maps the UART device to the on-board USB-UART
87+
class WithDatastormUART(rxdPin: String = "PIN_AG10", txdPin: String = "PIN_AH9") extends HarnessBinder({
88+
case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
89+
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[DatastormHarness]
90+
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
91+
harnessIO <> port.io
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val packagePinsWithPackageIOs = Seq(
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(rxdPin, IOPin(harnessIO.rxd)),
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(txdPin, IOPin(harnessIO.txd)))
95+
packagePinsWithPackageIOs foreach { case (pin, io) => {
96+
ath.io_tcl.addPackagePin(io, pin)
97+
ath.io_tcl.addIOStandard(io, "3.3-V LVTTL")
98+
} }
99+
}
100+
})
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102+
// Maps the UART device to PMOD JD pins 3/7
103+
class WithDatastormPMODUART extends WithDatastormUART("PIN_AB12", "PIN_AC12")
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class WithDatastormJTAG extends HarnessBinder({
106+
case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
107+
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[DatastormHarness]
108+
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
109+
harnessIO <> port.io
110+
111+
ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
112+
ath.sdc.addGroup(clocks = Seq("JTCK"))
113+
val packagePinsWithPackageIOs = Seq(
114+
("PIN_AD12", IOPin(harnessIO.TCK)),
115+
("PIN_AD10", IOPin(harnessIO.TMS)),
116+
("PIN_AC9", IOPin(harnessIO.TDI)),
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("PIN_AD9", IOPin(harnessIO.TDO))
118+
)
119+
packagePinsWithPackageIOs foreach { case (pin, io) => {
120+
ath.io_tcl.addPackagePin(io, pin)
121+
ath.io_tcl.addIOStandard(io, "3.3-V LVTTL")
122+
// TODO Check if Cyclone V devices have integrated pullups ath.io_tcl.addPullup(io)
123+
} }
124+
}
125+
})

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