Merge pull request #1973 from ucb-bar/ara-integrate

Integrate Ara vector unit

Author: jerryz123

.github/scripts/check-commit.sh

@@ -46,7 +46,7 @@ search () {
 }
 
 
-submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn")
+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara")
 dir="generators"
 branches=("master" "main" "dev")
 search

.github/scripts/defaults.sh

@@ -27,7 +27,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
-grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector"
+grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector chipyard-shuttleara"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
@@ -75,6 +75,7 @@ mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
 mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig"
 mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig"
 mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig"
+mapping["chipyard-shuttleara"]=" CONFIG=V4096Ara2LaneShuttleConfig USE_ARA=1 verilog"
 
 mapping["constellation"]=" SUB_PROJECT=constellation"
 mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig"

.github/scripts/run-tests.sh

@@ -144,6 +144,14 @@ case $1 in
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
         run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
         ;;
+    chipyard-shuttleara)
+        # Ara does not work with verilator
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-sgemm.riscv LOADMEM=1
+        # Ara cannot run strcmp
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-strcmp.riscv LOADMEM=1
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-daxpy.riscv LOADMEM=1
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-memcpy.riscv LOADMEM=1
+        ;;
     tracegen)
         run_tracegen
         ;;

.gitmodules

@@ -154,3 +154,6 @@
 [submodule "software/firesim-paper-workloads"]
 	path = software/firesim-paper-workloads
 	url = https://github.com/firesim/firesim-paper-workloads.git
+[submodule "generators/ara"]
+	path = generators/ara
+	url = https://github.com/ucb-bar/ara-wrapper.git

build.sbt

@@ -176,7 +176,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
-    compressacc, saturn)
+    compressacc, saturn, ara)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(
     libraryDependencies ++= Seq(
@@ -241,6 +241,11 @@ lazy val cva6 = (project in file("generators/cva6"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+lazy val ara = (project in file("generators/ara"))
+  .dependsOn(rocketchip, shuttle)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)
+
 lazy val ibex = (project in file("generators/ibex"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)

common.mk

@@ -64,6 +64,7 @@ HELP_COMMANDS += \
 #########################################################################################
 include $(base_dir)/generators/cva6/cva6.mk
 include $(base_dir)/generators/ibex/ibex.mk
+include $(base_dir)/generators/ara/ara.mk
 include $(base_dir)/generators/tracegen/tracegen.mk
 include $(base_dir)/generators/nvdla/nvdla.mk
 include $(base_dir)/tools/torture.mk

docs/Generators/Ara.rst

@@ -0,0 +1,16 @@
+Ara
+===
+
+`Ara <https://github.com/pulp-platform/ara>`__ is a RISC-V vector unit developed by the PULP project.
+The Ara vector unit supports integration with either the Rocket or Shuttle in-order cores, following a similar methodology as used in the original Ara+CVA6 system.
+Example Ara configurations are listed in ``generators/chipyard/src/main/scala/config/AraConfigs.scala``.
+
+.. Warning:: Ara only supports a partial subset of the full V-extension. Notably, we do not support virtual memory or precise traps with Ara.
+
+To compile simulators using Ara, you must pass an additional ``USE_ARA`` flag to the makefile.
+
+.. Note:: Ara only supports VCS for simulation
+
+.. code-block:: shell
+
+     make CONFIG=V4096Ara2LaneRocketConfig USE_ARA=1

docs/Generators/Saturn.rst

@@ -5,6 +5,7 @@ Saturn is a parameterized RISC-V Vector Unit generator currently supporting inte
 Saturn implements a compact short-vector-length vector microarchitecture suitable for deployment in a DSP-optimized core or area-efficient general-purpose core.
 
 More documentation on Saturn will be released in the future.
+A partial listing of supported Saturn configurations is in ``generators/chipyard/src/main/scala/config/SaturnConfigs.scala``.
 
  * Full support for `V` application-profile RVV 1.0
  * Precise traps with virtual memory

docs/Generators/index.rst

@@ -36,3 +36,4 @@ so changes to the generators themselves will automatically be used when building
    Mempress
    CompressAcc
    Prefetchers
+   Ara