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jerryz123jerryz123
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Only check for RISCV if running a make target that references it
1 parent 8f98d45 commit ebc836c

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4 files changed

+46
-39
lines changed

4 files changed

+46
-39
lines changed

‎common.mk‎

Lines changed: 32 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,21 @@
11
SHELL=/bin/bash
22
SED ?= sed
33

4-
ifndef RISCV
5-
$(error RISCV is unset. Did you source the Chipyard auto-generated env file (which activates the default conda environment)?)
6-
else
7-
$(info Running with RISCV=$(RISCV))
8-
endif
4+
# Note: Individual rules that use RISCV or external tools perform local checks to avoid
5+
# blocking unrelated targets. Use $(require_riscv) and $(call require_cmd,<tool>) inside recipes.
6+
7+
define require_riscv
8+
@if [ -z "$(RISCV)" ]; then \
9+
echo "RISCV is unset. Source env.sh (which activates the default conda env) before building sims." 1>&2; \
10+
exit 1; \
11+
fi
12+
endef
13+
14+
# Verify a tool is present in PATH; usage: $(call require_cmd,verilator)
15+
define require_cmd
16+
@command -v $(1) >/dev/null 2>&1 \
17+
|| { echo "Error: $(1) not found in PATH. Set up your tool environment before building this target." >&2; exit 1; }
18+
endef
919

1020
#########################################################################################
1121
# specify user-interface variables
@@ -184,27 +194,23 @@ else
184194
endif
185195

186196
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS)
187-
@# Ensure firtool is available before invoking CIRCT to emit Verilog
188-
@command -v firtool >/dev/null 2>&1 || { \
189-
echo "Error: firtool (CIRCT) not found in PATH. Install/activate CIRCT before running this target." >&2; \
190-
exit 1; \
191-
}
197+
$(call require_cmd,firtool)
192198
rm -rf $(GEN_COLLATERAL_DIR)
193199
(set -o pipefail && firtool \
194-
--format=fir \
195-
--export-module-hierarchy \
196-
--verify-each=true \
197-
--warn-on-unprocessed-annotations \
198-
--disable-annotation-classless \
199-
--disable-annotation-unknown \
200-
--mlir-timing \
201-
--lowering-options=$(shell cat $(MFC_LOWERING_OPTIONS)) \
202-
--repl-seq-mem \
203-
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
204-
--annotation-file=$(FINAL_ANNO_FILE) \
205-
--split-verilog \
206-
-o $(GEN_COLLATERAL_DIR) \
207-
$(FIRRTL_FILE) |& tee $(FIRTOOL_LOG_FILE))
200+
--format=fir \
201+
--export-module-hierarchy \
202+
--verify-each=true \
203+
--warn-on-unprocessed-annotations \
204+
--disable-annotation-classless \
205+
--disable-annotation-unknown \
206+
--mlir-timing \
207+
--lowering-options=$(shell cat $(MFC_LOWERING_OPTIONS)) \
208+
--repl-seq-mem \
209+
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
210+
--annotation-file=$(FINAL_ANNO_FILE) \
211+
--split-verilog \
212+
-o $(GEN_COLLATERAL_DIR) \
213+
$(FIRRTL_FILE) |& tee $(FIRTOOL_LOG_FILE))
208214
$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
209215
touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
210216
# DOC include end: FirrtlCompiler
@@ -395,8 +401,10 @@ run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(BINARY)
395401
$(output_dir):
396402
mkdir -p $@
397403

404+
ifdef RISCV
398405
$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% | $(output_dir)
399406
ln -sf $< $@
407+
endif
400408

401409
$(output_dir)/%.run: $(output_dir)/% $(SIM_PREREQ)
402410
(set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$<) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@

‎sims/vcs/Makefile‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -67,16 +67,17 @@ model_dir_debug = $(build_dir)/$(long_name).debug
6767
#########################################################################################
6868
# vcs simulator rules
6969
#########################################################################################
70-
.PHONY: check-vcs
71-
check-vcs:
72-
@command -v vcs >/dev/null 2>&1 \
73-
|| { echo "Error: Synopsys VCS not found in PATH. Set up your tool environment before building VCS sims." >&2; exit 1; }
7470

75-
$(sim): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) | check-vcs
71+
72+
$(sim): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
73+
$(call require_cmd,vcs)
74+
$(require_riscv)
7675
rm -rf $(model_dir)
7776
$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir)
7877

79-
$(sim_debug): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) | check-vcs
78+
$(sim_debug): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
79+
$(call require_cmd,vcs)
80+
$(require_riscv)
8081
rm -rf $(model_dir_debug)
8182
$(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir_debug) \
8283
+define+DEBUG -debug_access+all -kdb -lca

‎sims/verilator/Makefile‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -190,16 +190,14 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
190190
#########################################################################################
191191

192192
$(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
193-
@command -v verilator >/dev/null 2>&1 \
194-
|| { echo "Error: Verilator not found in PATH. Install or load it before building Verilator sims." >&2; exit 1; }
193+
$(call require_cmd,verilator)
195194
rm -rf $(model_dir)
196195
mkdir -p $(model_dir)
197196
$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
198197
touch $@
199198

200199
$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
201-
@command -v verilator >/dev/null 2>&1 \
202-
|| { echo "Error: Verilator not found in PATH. Install or load it before building Verilator sims." >&2; exit 1; }
200+
$(call require_cmd,verilator)
203201
rm -rf $(model_dir_debug)
204202
mkdir -p $(model_dir_debug)
205203
$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
@@ -209,9 +207,11 @@ $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
209207
# invoke make to make verilator sim rules
210208
#########################################################################################
211209
$(sim): $(model_mk) $(dramsim_lib)
210+
$(require_riscv)
212211
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
213212

214213
$(sim_debug): $(model_mk_debug) $(dramsim_lib)
214+
$(require_riscv)
215215
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
216216

217217
#########################################################################################

‎sims/xcelium/Makefile‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -80,12 +80,10 @@ model_dir_debug = $(build_dir)/$(long_name).debug
8080
#########################################################################################
8181
# xcelium simulator rules
8282
#########################################################################################
83-
.PHONY: check-xcelium
84-
check-xcelium:
85-
@command -v xrun >/dev/null 2>&1 \
86-
|| { echo "Error: Cadence Xcelium (xrun) not found in PATH. Set up your tool environment before building Xcelium sims." >&2; exit 1; }
8783

88-
$(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) | check-xcelium
84+
$(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
85+
$(call require_cmd,xrun)
86+
$(require_riscv)
8987
rm -rf $(model_dir)
9088
$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
9189

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