diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index be880e7b25..b189ce9bb1 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -46,7 +46,7 @@ search () { } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv" "tacit") +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv" "tacit" "radiance") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 812587db79..9bfc1d119a 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -25,7 +25,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle chipyard-shuttle3 chipyard-vexiiriscv chipyard-tacit-rocket" +grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle chipyard-shuttle3 chipyard-vexiiriscv chipyard-tacit-rocket chipyard-radiance" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc chipyard-rocketvector chipyard-shuttlevector chipyard-hlsacc" # chipyard-shuttleara - Add when Ara works again grouping["group-constellation"]="chipyard-constellation" @@ -80,6 +80,7 @@ mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig" mapping["chipyard-rocketvector"]=" CONFIG=MINV128D64RocketConfig" mapping["chipyard-shuttlevector"]=" CONFIG=GENV256D128ShuttleConfig" mapping["chipyard-shuttleara"]=" CONFIG=V4096Ara2LaneShuttleConfig USE_ARA=1 verilog" +mapping["chipyard-radiance"]=" CONFIG=RadianceFP16ClusterConfig verilog" mapping["constellation"]=" SUB_PROJECT=constellation" mapping["icenet"]="SUB_PROJECT=icenet" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index ea1bb78e2d..25410a4a89 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -173,6 +173,9 @@ case $1 in chipyard-tacit-rocket) run_binary LOADMEM=1 BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + chipyard-radiance) + # Verilator fails to build sim binary, just generate verilog + ;; icenet) run_binary BINARY=none ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 787352a9c0..82c30388fd 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -535,6 +535,29 @@ jobs: group-key: "group-cores" project-key: "chipyard-shuttle3" + chipyard-radiance-run-tests: + name: chipyard-radiance-run-tests + needs: prepare-chipyard-cores + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v4 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-cores" + project-key: "chipyard-radiance" + chipyard-tacit-rocket-run-tests: name: chipyard-tacit-rocket-run-tests needs: prepare-chipyard-cores diff --git a/.gitmodules b/.gitmodules index 90d327f8e1..e8eee4a8e4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -157,3 +157,6 @@ [submodule "generators/tacit"] path = generators/tacit url = https://github.com/ucb-bar/tacit.git +[submodule "generators/radiance"] + path = generators/radiance + url = https://github.com/ucb-bar/radiance.git diff --git a/build.sbt b/build.sbt index cb9e5709a8..d06d8780b2 100644 --- a/build.sbt +++ b/build.sbt @@ -156,7 +156,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache, dsptools, rocket_dsp_utils, - gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, + radiance, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, constellation, mempress, barf, shuttle, caliptra_aes, rerocc, compressacc, saturn, ara, firrtl2_bridge, vexiiriscv, tacit) .settings(libraryDependencies ++= rocketLibDeps.value) @@ -243,6 +243,17 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +lazy val radiance = (project in file("generators/radiance")) + .dependsOn(rocketchip, gemmini) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(libraryDependencies ++= Seq( + "edu.berkeley.cs" %% "chiseltest" % chiselTestVersion, + "org.scalatest" %% "scalatest" % "3.2.+" % "test", + "junit" % "junit" % "4.13" % "test", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test", + )) + .settings(commonSettings) + lazy val gemmini = freshProject("gemmini", file("generators/gemmini")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/common.mk b/common.mk index 6154602cc8..827eed6a1d 100644 --- a/common.mk +++ b/common.mk @@ -16,6 +16,8 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ " EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ +" EXTRA_SIM_OUT_NAME = additional suffix appended to the simulation .out log filename" \ +" EXTRA_SIM_PREPROC_DEFINES = additional Verilog preprocessor defines passed to the simulator" \ " ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \ @@ -26,6 +28,7 @@ EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= +EXTRA_SIM_OUT_NAME ?= ifneq ($(ASPECTS), ) comma = , @@ -67,6 +70,7 @@ include $(base_dir)/generators/ibex/ibex.mk include $(base_dir)/generators/ara/ara.mk include $(base_dir)/generators/tracegen/tracegen.mk include $(base_dir)/generators/nvdla/nvdla.mk +include $(base_dir)/generators/radiance/radiance.mk include $(base_dir)/tools/torture.mk ######################################################################################### @@ -233,6 +237,8 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS --model-module-name $(MODEL) \ --out-dut-smems-conf $(TOP_SMEMS_CONF) \ --out-model-smems-conf $(MODEL_SMEMS_CONF) +# for blackboxed SRAMs: add custom.mems.conf as blackbox and use generated module name in blackbox verilog source + -[ -f $(GEN_COLLATERAL_DIR)/custom.mems.conf ] && cat $(GEN_COLLATERAL_DIR)/custom.mems.conf >> $(TOP_SMEMS_CONF) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs TOP_MACROCOMPILER_MODE ?= --mode synflops @@ -256,7 +262,7 @@ ifneq (,$(EXT_FILELISTS)) else rm -f $@ endif - sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' >> $@ + sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\|conf\)$$' >> $@ echo "$(TOP_SMEMS_FILE)" >> $@ echo "$(MODEL_SMEMS_FILE)" >> $@ @@ -305,7 +311,7 @@ get_loadarch_flag = +loadarch=$(subst mem.elf,loadarch,$(1)) endif # get the output path base name for simulation outputs, First arg is the binary -get_sim_out_name = $(output_dir)/$(call get_out_name,$(1)) +get_sim_out_name = $(output_dir)/$(call get_out_name,$(1))$(if $(EXTRA_SIM_OUT_NAME),.$(EXTRA_SIM_OUT_NAME),) # sim flags that are common to run-binary/run-binary-fast/run-binary-debug get_common_sim_flags = $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(call get_loadmem_flag,$(1)) $(call get_loadarch_flag,$(1)) @@ -313,7 +319,7 @@ get_common_sim_flags = $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(call get_l # run normal binary with hardware-logged insn dissassembly run-binary: check-binary $(BINARY).run -run-binaries: check-binaries $(addsuffix .run,$(BINARIES)) +run-binaries: check-binaries $(addsuffix .run,$(wildcard $(BINARIES))) %.run: %.check-exists $(SIM_PREREQ) | $(output_dir) (set -o pipefail && $(NUMA_PREFIX) $(sim) \ @@ -327,7 +333,7 @@ run-binaries: check-binaries $(addsuffix .run,$(BINARIES)) # run simulator as fast as possible (no insn disassembly) run-binary-fast: check-binary $(BINARY).run.fast -run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES)) +run-binaries-fast: check-binaries $(addsuffix .run.fast,$(wildcard $(BINARIES))) %.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir) (set -o pipefail && $(NUMA_PREFIX) $(sim) \ @@ -340,7 +346,9 @@ run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES)) # run simulator with as much debug info as possible run-binary-debug: check-binary $(BINARY).run.debug -run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES)) +run-binary-debug-bg: check-binary $(BINARY).run.debug.bg +run-binaries-debug: check-binaries $(addsuffix .run.debug,$(wildcard $(BINARIES))) +run-binaries-debug-bg: check-binaries $(addsuffix .run.debug.bg,$(wildcard $(BINARIES))) %.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir) ifeq (1,$(DUMP_BINARY)) @@ -356,6 +364,19 @@ endif $(BINARY_ARGS) \ >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) +%.run.debug.bg: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir) + if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi + (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \ + $(PERMISSIVE_ON) \ + $(call get_common_sim_flags,$*) \ + $(VERBOSE_FLAGS) \ + $(call get_waveform_flag,$(call get_sim_out_name,$*)) \ + $(PERMISSIVE_OFF) \ + $* \ + $(BINARY_ARGS) \ + >(spike-dasm > $(call get_sim_out_name,$*).out) >$(call get_sim_out_name,$*).log \ + & echo "PID=$$!") + run-fast: run-asm-tests-fast run-bmark-tests-fast ######################################################################################### diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 618ba1de19..9815a89b68 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -32,6 +32,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port + with radiance.memory.CanHaveMemtraceCore // Enables memtrace core + with radiance.memory.CanHaveRadianceROMs // Enables radiance argument ROMs with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala new file mode 100644 index 0000000000..b6eb45a8d4 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala @@ -0,0 +1,20 @@ +package chipyard + +import org.chipsalliance.cde.config.{Config} +import freechips.rocketchip.prci.AsynchronousCrossing + +class MemtraceCoreConfig extends Config( + // Memtrace + new radiance.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", + traceHasSource = false) ++ + // new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", + // traceHasSource = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 8) ++ + // L2 + new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ + new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(16 * 8) ++ + new chipyard.NoCoresConfig + ) + diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala new file mode 100644 index 0000000000..e58217bcb2 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala @@ -0,0 +1,156 @@ +package chipyard + +import chipyard.stage.phases.TargetDirKey +import freechips.rocketchip.devices.tilelink.BootROMLocated +import freechips.rocketchip.resources.BigIntHexContext +import freechips.rocketchip.subsystem._ +import org.chipsalliance.cde.config.Config +import radiance.subsystem.RadianceGemminiDataType + +// ---------------- +// Radiance Configs +// ---------------- + +// aliases for virgo +class VirgoConfig extends RadianceClusterConfig +class VirgoFP16Config extends RadianceFP16ClusterConfig +class VirgoHopperConfig extends Radiance4CFP16ClusterConfig +class VirgoFlashConfig extends RadianceClusterConfig +class VirgoSynConfig extends RadianceClusterSynConfig +class VirgoFP16SynConfig extends RadianceFP16ClusterSynConfig +class VirgoHopperSynConfig extends Radiance4CFP16ClusterSynConfig + +class RadianceBaseConfig extends Config( + // NOTE: when changing these, remember to change NUM_CORES/THREADS/WARPS in + // the verilog source as well! + new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new freechips.rocketchip.subsystem.WithExtMemSize(BigInt("80000000", 16)) ++ + new chipyard.config.WithRadBootROM() ++ + new radiance.subsystem.WithRadianceSimParams(true) ++ + new freechips.rocketchip.subsystem.WithCacheBlockBytes(64) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ + new freechips.rocketchip.subsystem.WithEdgeDataBits(256) ++ + + new chipyard.config.WithPeripheryBusFrequency(400.0) ++ + new chipyard.config.WithMemoryBusFrequency(400.0) ++ + new chipyard.config.WithControlBusFrequency(400.0) ++ + new chipyard.config.WithSystemBusFrequency(400.0) ++ + new chipyard.config.WithFrontBusFrequency(400.0) ++ + new chipyard.config.WithOffchipBusFrequency(400.0) ++ + new chipyard.harness.WithHarnessBinderClockFreqMHz(400.0) ++ + new chipyard.config.AbstractConfig) + +class RadianceFP16ClusterConfig extends Config( + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++ + new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new RadianceBaseConfig) + +class Radiance8B8WFP16ClusterConfig extends Config( + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++ + new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 8, numWords = 8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new RadianceBaseConfig) + +class Radiance4CFP16ClusterConfig extends Config( + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++ + new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = true, useVxCache = false) ++ + // new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16, + // memType = radiance.subsystem.TwoReadOneWrite, + // serializeUnaligned = radiance.subsystem.CoreSerialized) ++ + // NOTE: Hopper Tensor Core does not work with 16-word config due to the + // address alignment requirement + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new RadianceBaseConfig) + +class RadianceClusterConfig extends Config( + // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ + new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = false, tensorCoreDecoupled = false, useVxCache = false) ++ + // new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 256 << 10/*KBytes*/, numBanks = 8, numWords = 8, + // memType = radiance.subsystem.TwoReadOneWrite, + serializeUnaligned = radiance.subsystem.CoreSerialized) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new RadianceBaseConfig) + +class RadianceClusterSmem16KConfig extends Config( + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++ + new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10/*KBytes*/, numBanks = 4, numWords = 8) ++ // serializeUnaligned: false + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new RadianceBaseConfig) + +class RadianceTwoClustersSmem16KConfig extends Config( + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++ + new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++ + new radiance.subsystem.WithRadianceGemmini(location = InCluster(1), dim = 8, accSizeInKB = 4, tileSize = 4) ++ + new radiance.subsystem.WithRadianceCores(2, location = InCluster(1), useVxCache = false) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10, numBanks = 4, numWords = 8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new radiance.subsystem.WithRadianceCluster(1) ++ + new RadianceBaseConfig) + +class RadianceBigLittleClusterConfig extends Config( + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 4, accSizeInKB = 16, tileSize = 16) ++ + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ + new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new RadianceBaseConfig) + +class RadianceClusterSynConfig extends Config( + new radiance.subsystem.WithRadianceSimParams(false) ++ + new RadianceClusterConfig) + +class RadianceFP16ClusterSynConfig extends Config( + new radiance.subsystem.WithRadianceSimParams(false) ++ + new RadianceFP16ClusterConfig) + +class Radiance4CFP16ClusterSynConfig extends Config( + new radiance.subsystem.WithRadianceSimParams(false) ++ + new Radiance4CFP16ClusterConfig) + +class RadianceBigLittleClusterSynConfig extends Config( + new radiance.subsystem.WithRadianceSimParams(false) ++ + new RadianceBigLittleClusterConfig) + +class RadianceNoCacheConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ + new RadianceBaseConfig) + +class RadianceNoCoalConfig extends Config( + new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ + new RadianceBaseConfig) + +class RadianceEmulatorConfig extends Config( + new radiance.subsystem.WithEmulatorCores(1, useVxCache = false) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 4) ++ + new chipyard.config.AbstractConfig) + +class RadianceFuzzerConfig extends Config( + new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ + new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 2) ++ + new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index a4931220cb..c0337f8d60 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -162,6 +162,16 @@ class WithNoBootROM extends Config((site, here, up) => { case BootROMLocated(_) => None }) +class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => { + case BootROMLocated(x) => up(BootROMLocated(x)) + .map(_.copy( + address = address, + size = size, + hang = hang, + contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv32.img" + )) +}) + class WithNoBusErrorDevices extends Config((site, here, up) => { case SystemBusKey => up(SystemBusKey).copy(errorDevice = None) case ControlBusKey => up(ControlBusKey).copy(errorDevice = None) diff --git a/generators/firechip/chip/src/main/scala/TargetConfigs.scala b/generators/firechip/chip/src/main/scala/TargetConfigs.scala index d61de2b39a..155a28429d 100644 --- a/generators/firechip/chip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/chip/src/main/scala/TargetConfigs.scala @@ -343,6 +343,14 @@ class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.LeanGemminiRocketConfig) +class FireSimRadianceClusterSynConfig extends Config( + new chipyard.harness.WithHarnessBinderClockFreqMHz(500.0) ++ + new chipyard.config.WithNoTraceIO ++ + new WithDefaultFireSimBridges ++ + new chipyard.config.WithRadBootROM ++ + new WithFireSimConfigTweaks ++ + new chipyard.RadianceClusterSynConfig) + class FireSimLargeBoomCospikeConfig extends Config( new WithCospikeBridge ++ new WithDefaultFireSimBridges ++ diff --git a/generators/gemmini b/generators/gemmini index 25809f7832..3b14b89c7f 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 25809f78323a729ef76fb68f3cedd8a24da2942b +Subproject commit 3b14b89c7f1d004fc4f03850706abdff76d007ce diff --git a/generators/radiance b/generators/radiance new file mode 160000 index 0000000000..29523c7845 --- /dev/null +++ b/generators/radiance @@ -0,0 +1 @@ +Subproject commit 29523c78458afcaa844a2f92814e15bffaef1d2f diff --git a/generators/rocket-chip b/generators/rocket-chip index c7aabd2823..7a2647d81e 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit c7aabd2823d3d001a7a9e8a982bb65d6cb7c9bdf +Subproject commit 7a2647d81e53e287a26b9e94c8ace9e765a97c41 diff --git a/generators/testchipip b/generators/testchipip index bf198d7fc2..fdbf1de6e7 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bf198d7fc23347d4151d7efad5d3db537efd0bb2 +Subproject commit fdbf1de6e752bbd9f245c94d9f1ea88a02fcedab diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 546c374cde..dd5130c476 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -38,4 +38,5 @@ SIM_PREPROC_DEFINES = \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN + +define+RANDOMIZE_INVALID_ASSIGN \ + $(EXTRA_SIM_PREPROC_DEFINES) diff --git a/variables.mk b/variables.mk index 9d6d678a33..03c9c8a52a 100644 --- a/variables.mk +++ b/variables.mk @@ -127,6 +127,29 @@ ifeq ($(SUB_PROJECT),constellation) TB ?= TestDriver TOP ?= NoC endif +# For graphics developers +ifeq ($(SUB_PROJECT),coalescer) + SBT_PROJECT ?= chipyard + MODEL ?= TestHarness + VLOG_MODEL ?= $(MODEL) + MODEL_PACKAGE ?= chipyard.unittest + CONFIG ?= CoalescingUnitTestConfig + CONFIG_PACKAGE ?= radiance.unittest + GENERATOR_PACKAGE ?= chipyard + TB ?= TestDriver + TOP ?= UnitTestSuite +endif +ifeq ($(SUB_PROJECT),tensor) + SBT_PROJECT ?= chipyard + MODEL ?= TestHarness + VLOG_MODEL ?= $(MODEL) + MODEL_PACKAGE ?= chipyard.unittest + CONFIG ?= TensorUnitTestConfig + CONFIG_PACKAGE ?= radiance.unittest + GENERATOR_PACKAGE ?= chipyard + TB ?= TestDriver + TOP ?= UnitTestSuite +endif ######################################################################################### @@ -195,7 +218,7 @@ EXT_FILELISTS ?= # external verilog incdirs. Users, or project-supplied make fragments can append to this EXT_INCDIRS ?= -BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img +BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img bootrom.radiance.rv32.img BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) # files that contain lists of files needed for VCS or Verilator simulation