diff --git a/common.mk b/common.mk
index 827eed6a1d..a42a05360e 100644
--- a/common.mk
+++ b/common.mk
@@ -23,7 +23,7 @@ HELP_COMPILATION_VARIABLES += \
 "   MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \
 "   ASPECTS                   = comma separated list of Chisel aspect flows to run (e.x. chipyard.upf.ChipTopUPFAspect)"
 
-EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS)
+EXTRA_GENERATOR_REQS ?=
 EXTRA_SIM_CXXFLAGS   ?=
 EXTRA_SIM_LDFLAGS    ?=
 EXTRA_SIM_SOURCES    ?=
@@ -104,15 +104,9 @@ TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS
 SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators tools)
 SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties
 
-#########################################################################################
-# copy over bootrom files
-#########################################################################################
 $(build_dir):
 	mkdir -p $@
 
-$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir)
-	cp -f $< $@
-
 #########################################################################################
 # compile scala jars
 #########################################################################################
diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
index 1090f459ec..6fa0c00932 100644
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -8,6 +8,7 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
 import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
 import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
+import freechips.rocketchip.util.{SystemFileName}
 
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -32,7 +33,7 @@ class WithSystemModifications extends Config((site, here, up) => {
     val freqMHz = (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toLong
     val make = s"make -C fpga/src/main/resources/vc707/sdboot PBUS_CLK=${freqMHz} bin"
     require (make.! == 0, "Failed to build bootrom")
-    p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
+    p.copy(hang = 0x10000, contentFileName = SystemFileName(s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin"))
   }
   case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size)
   case SerialTLKey => Nil // remove serialized tl port
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index 460cea72d1..1ab72f1dba 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -8,6 +8,7 @@ import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
 import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
 import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
+import freechips.rocketchip.util.{SystemFileName}
 
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
@@ -33,7 +34,7 @@ class WithSystemModifications extends Config((site, here, up) => {
     val freqMHz = (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toLong
     val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin"
     require (make.! == 0, "Failed to build bootrom")
-    p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
+    p.copy(hang = 0x10000, contentFileName = SystemFileName(s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin"))
   }
   case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
   case SerialTLKey => Nil // remove serialized tl port
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 9815a89b68..6183a5e8d4 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -33,7 +33,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
   with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
   with radiance.memory.CanHaveMemtraceCore // Enables memtrace core
-  with radiance.memory.CanHaveRadianceROMs // Enables radiance argument ROMs
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
   with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
index c0337f8d60..cf1af46329 100644
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -10,6 +10,7 @@ import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, D
 import freechips.rocketchip.prci.{AsynchronousCrossing}
 import chipyard.stage.phases.TargetDirKey
 import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util.{ResourceFileName}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -35,7 +36,7 @@ class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt =
         address = address,
         size = size,
         hang = hang,
-        contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(MaxXLen)}.img"
+        contentFileName = ResourceFileName(s"/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img")
       ))
 })
 
@@ -159,7 +160,7 @@ class WithNoCLINT extends Config((site, here, up) => {
 })
 
 class WithNoBootROM extends Config((site, here, up) => {
-  case BootROMLocated(_) => None
+  case BootROMLocated(_) => Nil
 })
 
 class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => {
@@ -168,7 +169,7 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
       address = address,
       size = size,
       hang = hang,
-      contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv32.img"
+      contentFileName = ResourceFileName(s"/testchipip/bootrom/bootrom.radiance.rv32.img")
     ))
 })
 
diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index acaf171f42..1e34c3f8dc 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -506,7 +506,7 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
         maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0),
         pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),
         nharts = tiles.size,
-        bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
+        bootrom = chipyardSystem.bootROM.headOption.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
         has_dtm = useSimDTM,
         mems = mems,
         // Connect using the legacy API for firesim only
diff --git a/generators/cva6 b/generators/cva6
index 44c30fda2d..17e9b5119f 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 44c30fda2d1b7e87172b6372b12ce2cfdf328c60
+Subproject commit 17e9b5119f2e7021f1bce67f2601dedc5bfecc5c
diff --git a/generators/firechip/chip/src/main/scala/TargetConfigs.scala b/generators/firechip/chip/src/main/scala/TargetConfigs.scala
index 155a28429d..879ac198b6 100644
--- a/generators/firechip/chip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/chip/src/main/scala/TargetConfigs.scala
@@ -20,20 +20,6 @@ import icenet._
 import chipyard.clocking.{ChipyardPRCIControlKey}
 import chipyard.harness.{HarnessClockInstantiatorKey}
 
-class WithBootROM extends Config((site, here, up) => {
-  case BootROMLocated(x) => {
-    val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img")
-    val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(MaxXLen)}.img")
-
-    val bootROMPath = if (chipyardBootROM.exists()) {
-      chipyardBootROM.getAbsolutePath()
-    } else {
-      firesimBootROM.getAbsolutePath()
-    }
-    up(BootROMLocated(x)).map(_.copy(contentFileName = bootROMPath))
-  }
-})
-
 // Disables clock-gating; doesn't play nice with our FAME-1 pass
 class WithoutClockGating extends Config((site, here, up) => {
   case DebugModuleKey => up(DebugModuleKey).map(_.copy(clockGate = false))
@@ -76,8 +62,6 @@ class WithMinimalFireSimDesignTweaks extends Config(
   new chipyard.harness.WithResetFromHarness ++
   new chipyard.config.WithNoClockTap ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
-  new WithBootROM ++
   // Required: Existing FAME-1 transform cannot handle black-box clock gates
   new WithoutClockGating ++
   // Optional: Do not support debug module w. JTAG until FIRRTL stops emitting @(posedge ~clock)
@@ -240,7 +224,6 @@ class FireSimQuadRocketConfig extends Config(
 // Flat to avoid having to reorganize the config class hierarchy to remove certain features
 class FireSimSmallSystemConfig extends Config(
   new WithDefaultFireSimBridges ++
-  new WithBootROM ++
   new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
   new chipyard.config.WithControlBusFrequency(3200.0) ++
   new chipyard.config.WithSystemBusFrequency(3200.0) ++
diff --git a/generators/radiance b/generators/radiance
index b79f12950b..81ce07ce10 160000
--- a/generators/radiance
+++ b/generators/radiance
@@ -1 +1 @@
-Subproject commit b79f12950b9453b6bd23aa5d0c96dcd2e4f2e554
+Subproject commit 81ce07ce1079ec1d34bb3f233b9eb8d903e1ef05
diff --git a/generators/rocket-chip b/generators/rocket-chip
index a54937e6e7..337f2abf57 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit a54937e6e73d762e3d9ed811155edee3ba24a8c1
+Subproject commit 337f2abf57f38a16c7354704020587c98035d337
diff --git a/variables.mk b/variables.mk
index 03c9c8a52a..d5b0f5770c 100644
--- a/variables.mk
+++ b/variables.mk
@@ -218,9 +218,6 @@ EXT_FILELISTS ?=
 # external verilog incdirs. Users, or project-supplied make fragments can append to this
 EXT_INCDIRS ?=
 
-BOOTROM_FILES   ?= bootrom.rv64.img bootrom.rv32.img bootrom.radiance.rv32.img
-BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
-
 # files that contain lists of files needed for VCS or Verilator simulation
 SIM_FILE_REQS =
 sim_files              ?= $(build_dir)/sim_files.f