diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index cc23a8c87d..f177a1667a 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -150,6 +150,7 @@ jobs:
       - name: Check that documentation builds with no warnings/errors
         run: |
           conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)
+          scripts/init-submodules-no-riscv-tools.sh --full
           make -C docs html
       - name: Show error log from sphinx if failed
         if: ${{ failure() }}
diff --git a/build.sbt b/build.sbt
index ae8b585720..83ac3d622a 100644
--- a/build.sbt
+++ b/build.sbt
@@ -148,7 +148,7 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 
 // -- Chipyard-managed External Projects --
 
-lazy val testchipip = (project in file("generators/testchipip"))
+lazy val testchipip = withInitCheck((project in file("generators/testchipip")), "testchipip")
   .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -160,9 +160,9 @@ lazy val chipyard = {
     .dependsOn(
       testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
       dsptools, rocket_dsp_utils,
-      radiance, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
+      icenet, tracegen,
       constellation, barf, shuttle, rerocc,
-      firrtl2_bridge, vexiiriscv, tacit
+      firrtl2_bridge
     )
     .settings(libraryDependencies ++= rocketLibDeps.value)
     .settings(
@@ -175,11 +175,21 @@ lazy val chipyard = {
 
   // Optional modules discovered via initialized submodules (no env or manifest)
   val optionalModules: Seq[(String, ProjectReference)] = Seq(
+    // Generators with Chipyard-facing glue compiled from their repos
+    "cva6" -> cva6,
+    "ibex" -> ibex,
+    "vexiiriscv" -> vexiiriscv,
+    "riscv-sodor" -> sodor,
     "ara" -> ara,
     "saturn" -> saturn,
+    "tacit" -> tacit,
+    "gemmini" -> gemmini,
+    "nvdla" -> nvdla,
+    "radiance" -> radiance,
     "caliptra-aes-acc" -> caliptra_aes,
     "compress-acc" -> compressacc,
-    "mempress" -> mempress
+    "mempress" -> mempress,
+    "fft-generator" -> fft_generator
   )
 
   // Discover optional modules if their submodule is initialized
@@ -205,32 +215,32 @@ lazy val chipyard = {
   cy
 }
 
-lazy val compressacc = (project in file("generators/compress-acc"))
+lazy val compressacc = withInitCheck((project in file("generators/compress-acc")), "compress-acc")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val mempress = (project in file("generators/mempress"))
+lazy val mempress = withInitCheck((project in file("generators/mempress")), "mempress")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val barf = (project in file("generators/bar-fetchers"))
+lazy val barf = withInitCheck((project in file("generators/bar-fetchers")), "bar-fetchers")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val saturn = (project in file("generators/saturn"))
+lazy val saturn = withInitCheck((project in file("generators/saturn")), "saturn")
   .dependsOn(rocketchip, shuttle)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val constellation = (project in file("generators/constellation"))
+lazy val constellation = withInitCheck((project in file("generators/constellation")), "constellation")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val fft_generator = (project in file("generators/fft-generator"))
+lazy val fft_generator = withInitCheck((project in file("generators/fft-generator")), "fft-generator")
   .dependsOn(rocketchip, rocket_dsp_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -240,7 +250,7 @@ lazy val tracegen = (project in file("generators/tracegen"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val icenet = (project in file("generators/icenet"))
+lazy val icenet = withInitCheck((project in file("generators/icenet")), "icenet")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -250,37 +260,57 @@ lazy val boom = freshProject("boom", file("generators/boom"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val shuttle = (project in file("generators/shuttle"))
+lazy val shuttle = withInitCheck((project in file("generators/shuttle")), "shuttle")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val cva6 = (project in file("generators/cva6"))
+// Helper: fail fast if a generator project is used without its submodule initialized.
+def withInitCheck(p: Project, genDirName: String): Project = {
+  val checkTask = Def.task {
+    val root = (ThisBuild / baseDirectory).value
+    val dir = root / s"generators/$genDirName"
+    val looksInitialized = (dir / ".git").exists
+    if (!dir.exists || !looksInitialized) {
+      sys.error(
+        s"Generator '$genDirName' is not initialized at '" + dir.getAbsolutePath +
+        "'. Run scripts/build-setup.sh or init the submodule (scripts/init-submodules-no-riscv-tools-nolog.sh).")
+    }
+  }
+  p.settings(
+    // Run the check whenever this project's code is compiled/tested/run
+    Compile / compile := (Compile / compile).dependsOn(checkTask).value,
+    Test / compile := (Test / compile).dependsOn(checkTask).value,
+    Compile / run := (Compile / run).dependsOn(checkTask).evaluated
+  )
+}
+
+lazy val cva6 = withInitCheck((project in file("generators/cva6")), "cva6")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val ara = (project in file("generators/ara"))
+lazy val ara = withInitCheck((project in file("generators/ara")), "ara")
   .dependsOn(rocketchip, shuttle)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val ibex = (project in file("generators/ibex"))
+lazy val ibex = withInitCheck((project in file("generators/ibex")), "ibex")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val vexiiriscv = (project in file("generators/vexiiriscv"))
+lazy val vexiiriscv = withInitCheck((project in file("generators/vexiiriscv")), "vexiiriscv")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val sodor = (project in file("generators/riscv-sodor"))
+lazy val sodor = withInitCheck((project in file("generators/riscv-sodor")), "riscv-sodor")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val radiance = (project in file("generators/radiance"))
+lazy val radiance = withInitCheck((project in file("generators/radiance")), "radiance")
   .dependsOn(rocketchip, gemmini, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(libraryDependencies ++= Seq(
@@ -291,32 +321,32 @@ lazy val radiance = (project in file("generators/radiance"))
   ))
   .settings(commonSettings)
 
-lazy val gemmini = freshProject("gemmini", file("generators/gemmini"))
+lazy val gemmini = withInitCheck(freshProject("gemmini", file("generators/gemmini")), "gemmini")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val nvdla = (project in file("generators/nvdla"))
+lazy val nvdla = withInitCheck((project in file("generators/nvdla")), "nvdla")
   .dependsOn(rocketchip, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val tacit = (project in file("generators/tacit"))
+lazy val tacit = withInitCheck((project in file("generators/tacit")), "tacit")
   .dependsOn(rocketchip, shuttle, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
+lazy val caliptra_aes = withInitCheck((project in file("generators/caliptra-aes-acc")), "caliptra-aes-acc")
   .dependsOn(rocketchip, rocc_acc_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rerocc = (project in file("generators/rerocc"))
+lazy val rerocc = withInitCheck((project in file("generators/rerocc")), "rerocc")
   .dependsOn(rocketchip, constellation, boom, shuttle)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
+lazy val rocc_acc_utils = withInitCheck((project in file("generators/rocc-acc-utils")), "rocc-acc-utils")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -354,12 +384,12 @@ lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocke
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rocketchip_blocks = (project in file("generators/rocket-chip-blocks"))
+lazy val rocketchip_blocks = withInitCheck((project in file("generators/rocket-chip-blocks")), "rocket-chip-blocks")
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-inclusive-cache"))
+lazy val rocketchip_inclusive_cache = withInitCheck((project in file("generators/rocket-chip-inclusive-cache")), "rocket-chip-inclusive-cache")
   .settings(
     commonSettings,
     Compile / scalaSource := baseDirectory.value / "design/craft")
diff --git a/common.mk b/common.mk
index 99d37f93b4..8de57f3b75 100644
--- a/common.mk
+++ b/common.mk
@@ -68,8 +68,7 @@ HELP_COMMANDS += \
 "   run-tests                   = run all assembly and benchmark tests" \
 "   launch-sbt                  = start sbt terminal" \
 "   find-configs                = list Chipyard Config classes (eligible CONFIG=)" \
-"   find-config-fragments       = list all config. fragments" \
-"   check-submodule-status      = check that all submodules in generators/ have been initialized"
+"   find-config-fragments       = list all config. fragments"
 
 #########################################################################################
 # include additional subproject make fragments
@@ -78,10 +77,6 @@ HELP_COMMANDS += \
 include $(base_dir)/generators/tracegen/tracegen.mk
 include $(base_dir)/tools/torture.mk
 # Optional generator make fragments should not fail build if absent
--include $(base_dir)/generators/cva6/cva6.mk
--include $(base_dir)/generators/ibex/ibex.mk
--include $(base_dir)/generators/nvdla/nvdla.mk
--include $(base_dir)/generators/radiance/radiance.mk
 # Wildcard include for standardized per-generator make fragments
 -include $(wildcard $(base_dir)/generators/*/chipyard.mk)
 
@@ -100,8 +95,6 @@ endif
 # Returns a list of files in directories $1 with *any* of the file extensions in $2
 lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type)))
 
-CHECK_SUBMODULES_COMMAND = echo "Checking required submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep '^-.*' | grep -vE "(ara|caliptra|compress|mempress|saturn)"
-
 SCALA_EXT = scala
 VLOG_EXT = sv v
 FIRESIM_SOURCE_DIRS = $(addprefix sims/firesim/,sim/firesim-lib sim/midas/targetutils) $(addprefix generators/firechip/,chip bridgeinterfaces bridgestubs) tools/firrtl2
@@ -124,7 +117,6 @@ $(build_dir):
 # compile scala jars
 #########################################################################################
 $(GENERATOR_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
-	$(CHECK_SUBMODULES_COMMAND)
 	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,$(SBT_PROJECT),$(GENERATOR_CLASSPATH))
 
@@ -460,14 +452,6 @@ find-configs:
 help:
 	@for line in $(HELP_LINES); do echo "$$line"; done
 
-#########################################################################################
-# Check submodule status
-#########################################################################################
-
-.PHONY: check-submodule-status
-check-submodule-status:
-	$(CHECK_SUBMODULES_COMMAND)
-
 #########################################################################################
 # Implicit rule handling
 #########################################################################################
diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst
index 818d7b695d..3416f91df0 100644
--- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst
+++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst
@@ -123,3 +123,11 @@ Another description of traits/mixins and config fragments is given in :ref:`Cust
 Additionally, a brief explanation of some of these topics (with slightly different naming) is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY.
 
 .. Note:: Chipyard uses the name "config fragments" over "config mixins" to avoid confusion between a mixin applying to a config or to the system ``Top`` (even though both are technically Scala mixins).
+
+Optional Generator Injectors
+----------------------------
+
+Some generic Chipyard config fragments (for example, trace toggles and tile prefetch settings) are designed to affect optional generators without hard dependencies. Chipyard discovers generator-provided injectors at elaboration time and applies them, allowing fragments like ``WithTraceIO`` and ``WithTilePrefetchers`` to work across different tiles.
+
+- Generators that want to participate implement ``chipyard.config.TilePluginProvider`` under their ``generators/<name>/chipyard`` sources. Chipyard discovers implementations via classpath scanning and applies the provided injectors.
+- This keeps the core fragments generic, while enabling per-generator behavior (e.g., mapping a prefetch intent to the correct port parameters for that tile).
diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
index fe2e613795..9922646357 100644
--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -97,6 +97,8 @@ See ``./build-setup.sh --help`` for more details on what this does and how to di
 
 .. Note:: If you already have a working conda environment setup, separate Chipyard clones can use that pre-used environment in combination with running the aforementioned scripts yourself (``init-submodules...``, ``build-toolchain...``, etc).
 
+.. Note for power users: Chipyard includes internal scripts that can selectively initialize generator submodules. The default ``./build-setup.sh`` initializes all standard generator submodules and is the recommended path.
+
 .. Note:: If you are a power user and would like to build your own compiler/toolchain, you can refer to the https://github.com/ucb-bar/riscv-tools-feedstock repository (submoduled in the ``toolchains/*`` directories) on how to build the compiler yourself.
 
 By running the following command you should see an environment listed with the path ``$CHIPYARD_DIRECTORY/.conda-env``.
diff --git a/docs/Generators/CVA6.rst b/docs/Generators/CVA6.rst
index bfca746a0a..238021db50 100644
--- a/docs/Generators/CVA6.rst
+++ b/docs/Generators/CVA6.rst
@@ -2,13 +2,19 @@ CVA6 Core
 ====================================
 
 `CVA6 <https://github.com/openhwgroup/cva6>`__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini.
-The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
+The `CVA6 core` is wrapped in a `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`.
 The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
 
 .. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface).
 
 While the core itself is not a generator, we expose the same parameterization that the CVA6 core provides (i.e. change branch prediction parameters).
 
+Configuration classes and Chipyard glue for CVA6 live under ``generators/cva6/chipyard`` and are compiled directly from the CVA6 repository sources. After running the standard setup (``./build-setup.sh``), you can build a CVA6 config like ``CVA6Config`` with the normal flow:
+
+::
+
+  cd sims/vcs && make CONFIG=CVA6Config
+
 .. Warning::  This target does not support Verilator simulation at this time. Please use VCS.
 
 For more information, please refer to the `GitHub repository <https://github.com/openhwgroup/cva6>`__.
diff --git a/docs/Generators/Ibex.rst b/docs/Generators/Ibex.rst
index ede74378d4..aa0d1ed2ed 100644
--- a/docs/Generators/Ibex.rst
+++ b/docs/Generators/Ibex.rst
@@ -9,6 +9,12 @@ The core exposes a custom memory interface, interrupt ports, and other misc. por
 
 .. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80.
 
-While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
-
+While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
+
 For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.
+
+Configuration classes and Chipyard glue for Ibex live under ``generators/ibex/chipyard`` and are compiled directly from the Ibex repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
+
+::
+
+  cd sims/vcs && make CONFIG=IbexConfig
diff --git a/docs/Generators/Sodor.rst b/docs/Generators/Sodor.rst
index 41d030da0b..00a96982b1 100644
--- a/docs/Generators/Sodor.rst
+++ b/docs/Generators/Sodor.rst
@@ -15,3 +15,9 @@ The five available cores and their corresponding generator configuration are:
 * "bus"-based micro-coded implementation - ``SodorUCodeConfig``
 
 For more information, please refer to the `GitHub repository <https://github.com/ucb-bar/riscv-sodor>`__.
+
+Configuration classes and Chipyard glue for Sodor live under ``generators/riscv-sodor/chipyard`` and are compiled directly from the Sodor repository sources. After running the standard setup (``./build-setup.sh``), build a config (e.g., 3-stage) with:
+
+::
+
+  cd sims/vcs && make CONFIG=Sodor3StageConfig
diff --git a/docs/Generators/VexiiRiscv.rst b/docs/Generators/VexiiRiscv.rst
index 358f90d773..e215be12d1 100644
--- a/docs/Generators/VexiiRiscv.rst
+++ b/docs/Generators/VexiiRiscv.rst
@@ -7,3 +7,8 @@ VexiiRiscv implements cache-coherent TileLink L1 data caches and is integrated a
 The example VexiiRiscv config is ``VexiiRiscvConfig``.
 When building this Config, Chipyard will call VexiiRiscv's SpinalHDL RTL generator to generate the core's SystemVerilog, before integrating it as a Chisel blackbox.
 
+Configuration classes and Chipyard glue for VexiiRiscv live under ``generators/vexiiriscv/chipyard`` and are compiled directly from the VexiiRiscv repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:
+
+::
+
+  cd sims/vcs && make CONFIG=VexiiRiscvConfig
diff --git a/docs/Generators/fft.rst b/docs/Generators/fft.rst
index 3cdaf23835..a51724dea0 100644
--- a/docs/Generators/fft.rst
+++ b/docs/Generators/fft.rst
@@ -7,7 +7,7 @@ Configuration
 --------------------------
 The following configuration creates an 8-point FFT:
 
-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+.. literalinclude:: ../../generators/fft-generator/chipyard/FFTConfigs.scala
    :language: scala
    :start-after: DOC include start: FFTRocketConfig
    :end-before: DOC include end: FFTRocketConfig
diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala
deleted file mode 100644
index 7b4406c4d1..0000000000
--- a/generators/chipyard/src/main/scala/config/CVA6Configs.scala
+++ /dev/null
@@ -1,19 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import org.chipsalliance.cde.config.{Config}
-
-// ---------------------
-// CVA6 Configs
-// ---------------------
-
-class CVA6Config extends Config(
-  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
-  new chipyard.config.AbstractConfig)
-
-class dmiCVA6Config extends Config(
-  new chipyard.harness.WithSerialTLTiedOff ++      // Tie off the serial-tilelink port
-  new chipyard.config.WithDMIDTM ++                // have debug module expose a clocked DMI port
-  new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
-  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
deleted file mode 100644
index b6eb45a8d4..0000000000
--- a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala
+++ /dev/null
@@ -1,20 +0,0 @@
-package chipyard
-
-import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.prci.AsynchronousCrossing
-
-class MemtraceCoreConfig extends Config(
-  // Memtrace
-  new radiance.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace",
-    traceHasSource = false) ++
-  // new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace",
-  //   traceHasSource = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 8) ++
-  // L2
-  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
-  new freechips.rocketchip.subsystem.WithNBanks(4) ++
-  new chipyard.config.WithSystemBusWidth(16 * 8) ++
-  new chipyard.NoCoresConfig
-  )
-
diff --git a/generators/chipyard/src/main/scala/config/IbexConfigs.scala b/generators/chipyard/src/main/scala/config/IbexConfigs.scala
deleted file mode 100644
index 7d472af526..0000000000
--- a/generators/chipyard/src/main/scala/config/IbexConfigs.scala
+++ /dev/null
@@ -1,16 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import org.chipsalliance.cde.config.{Config}
-
-// ---------------------
-// Ibex Configs
-// ---------------------
-
-// Multi-core and 32b heterogeneous configs are supported
-
-class IbexConfig extends Config(
-  new ibex.WithNIbexCores(1) ++
-  new chipyard.config.WithInclusiveCacheWriteBytes(4) ++
-  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
index e2587cf5f8..5a1497a2b9 100644
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -6,13 +6,6 @@ import org.chipsalliance.cde.config.{Config}
 // Configs with MMIO accelerators
 // ------------------------------
 
-// DOC include start: FFTRocketConfig
-class FFTRocketConfig extends Config(
-  new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: FFTRocketConfig
-
 // DOC include start: GCDTLRocketConfig
 class GCDTLRocketConfig extends Config(
   new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
@@ -56,20 +49,3 @@ class StreamingFIRRocketConfig extends Config (
   new chipyard.config.AbstractConfig)
 // DOC include end: StreamingFIRRocketConfig
 
-class SmallNVDLARocketConfig extends Config(
-  new nvidia.blocks.dla.WithNVDLA("small") ++               // add a small NVDLA
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.AbstractConfig)
-
-class LargeNVDLARocketConfig extends Config(
-  new nvidia.blocks.dla.WithNVDLA("large", true) ++         // add a large NVDLA with synth. rams
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.AbstractConfig)
-
-class ManyMMIOAcceleratorRocketConfig extends Config(
-  new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++   // add InitZero
-  new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
-  new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
-  new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
deleted file mode 100644
index e58217bcb2..0000000000
--- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala
+++ /dev/null
@@ -1,156 +0,0 @@
-package chipyard
-
-import chipyard.stage.phases.TargetDirKey
-import freechips.rocketchip.devices.tilelink.BootROMLocated
-import freechips.rocketchip.resources.BigIntHexContext
-import freechips.rocketchip.subsystem._
-import org.chipsalliance.cde.config.Config
-import radiance.subsystem.RadianceGemminiDataType
-
-// ----------------
-// Radiance Configs
-// ----------------
-
-// aliases for virgo
-class VirgoConfig extends RadianceClusterConfig
-class VirgoFP16Config extends RadianceFP16ClusterConfig
-class VirgoHopperConfig extends Radiance4CFP16ClusterConfig
-class VirgoFlashConfig extends RadianceClusterConfig
-class VirgoSynConfig extends RadianceClusterSynConfig
-class VirgoFP16SynConfig extends RadianceFP16ClusterSynConfig
-class VirgoHopperSynConfig extends Radiance4CFP16ClusterSynConfig
-
-class RadianceBaseConfig extends Config(
-  // NOTE: when changing these, remember to change NUM_CORES/THREADS/WARPS in
-  // the verilog source as well!
-  new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new freechips.rocketchip.subsystem.WithExtMemSize(BigInt("80000000", 16)) ++
-  new chipyard.config.WithRadBootROM() ++
-  new radiance.subsystem.WithRadianceSimParams(true) ++
-  new freechips.rocketchip.subsystem.WithCacheBlockBytes(64) ++
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++
-  new freechips.rocketchip.subsystem.WithEdgeDataBits(256) ++
-
-  new chipyard.config.WithPeripheryBusFrequency(400.0) ++
-  new chipyard.config.WithMemoryBusFrequency(400.0) ++
-  new chipyard.config.WithControlBusFrequency(400.0) ++
-  new chipyard.config.WithSystemBusFrequency(400.0) ++
-  new chipyard.config.WithFrontBusFrequency(400.0) ++
-  new chipyard.config.WithOffchipBusFrequency(400.0) ++
-  new chipyard.harness.WithHarnessBinderClockFreqMHz(400.0) ++
-  new chipyard.config.AbstractConfig)
-
-class RadianceFP16ClusterConfig extends Config(
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
-  new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++
-  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new RadianceBaseConfig)
-
-class Radiance8B8WFP16ClusterConfig extends Config(
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
-  new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++
-  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 8, numWords = 8) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new RadianceBaseConfig)
-
-class Radiance4CFP16ClusterConfig extends Config(
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
-  new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = true, useVxCache = false) ++
-  // new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16,
-  //                                              memType = radiance.subsystem.TwoReadOneWrite,
-  //                                              serializeUnaligned = radiance.subsystem.CoreSerialized) ++
-  // NOTE: Hopper Tensor Core does not work with 16-word config due to the
-  // address alignment requirement
-  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 8) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new RadianceBaseConfig)
-
-class RadianceClusterConfig extends Config(
-  // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
-  new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = false, tensorCoreDecoupled = false, useVxCache = false) ++
-  // new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++
-  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 256 << 10/*KBytes*/, numBanks = 8, numWords = 8,
-                                               // memType = radiance.subsystem.TwoReadOneWrite,
-                                               serializeUnaligned = radiance.subsystem.CoreSerialized) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new RadianceBaseConfig)
-
-class RadianceClusterSmem16KConfig extends Config(
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++
-  new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++
-  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10/*KBytes*/, numBanks = 4, numWords = 8) ++ // serializeUnaligned: false
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new RadianceBaseConfig)
-
-class RadianceTwoClustersSmem16KConfig extends Config(
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++
-  new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(1), dim = 8, accSizeInKB = 4, tileSize = 4) ++
-  new radiance.subsystem.WithRadianceCores(2, location = InCluster(1), useVxCache = false) ++
-  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10, numBanks = 4, numWords = 8) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new radiance.subsystem.WithRadianceCluster(1) ++
-  new RadianceBaseConfig)
-
-class RadianceBigLittleClusterConfig extends Config(
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 4, accSizeInKB = 16, tileSize = 16) ++
-  new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++
-  new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++
-  new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++
-  new radiance.subsystem.WithRadianceCluster(0) ++
-  new RadianceBaseConfig)
-
-class RadianceClusterSynConfig extends Config(
-  new radiance.subsystem.WithRadianceSimParams(false) ++
-  new RadianceClusterConfig)
-
-class RadianceFP16ClusterSynConfig extends Config(
-  new radiance.subsystem.WithRadianceSimParams(false) ++
-  new RadianceFP16ClusterConfig)
-
-class Radiance4CFP16ClusterSynConfig extends Config(
-  new radiance.subsystem.WithRadianceSimParams(false) ++
-  new Radiance4CFP16ClusterConfig)
-
-class RadianceBigLittleClusterSynConfig extends Config(
-  new radiance.subsystem.WithRadianceSimParams(false) ++
-  new RadianceBigLittleClusterConfig)
-
-class RadianceNoCacheConfig extends Config(
-  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++
-  new RadianceBaseConfig)
-
-class RadianceNoCoalConfig extends Config(
-  new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++
-  new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++
-  new RadianceBaseConfig)
-
-class RadianceEmulatorConfig extends Config(
-  new radiance.subsystem.WithEmulatorCores(1, useVxCache = false) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 4) ++
-  new chipyard.config.AbstractConfig)
-
-class RadianceFuzzerConfig extends Config(
-  new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++
-  new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++
-  new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 2) ++
-  new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
-  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
index 8256de7113..2f8f15a6ad 100644
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -6,32 +6,6 @@ import org.chipsalliance.cde.config.{Config}
 // Configs with RoCC Accelerators
 // ------------------------------
 
-// DOC include start: GemminiRocketConfig
-class GemminiRocketConfig extends Config(
-  new gemmini.DefaultGemminiConfig ++                            // use Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: GemminiRocketConfig
-
-class FPGemminiRocketConfig extends Config(
-  new gemmini.GemminiFP32DefaultConfig ++                         // use FP32Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
-class LeanGemminiRocketConfig extends Config(
-  new gemmini.LeanGemminiConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
-class LeanGemminiPrintfRocketConfig extends Config(
-  new gemmini.LeanGemminiPrintfConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.WithSystemBusWidth(128) ++
-  new chipyard.config.AbstractConfig)
-
 class ReRoCCTestConfig extends Config(
   new rerocc.WithReRoCC ++
   new chipyard.config.WithCharacterCountRoCC ++                // rerocc tile4 is charcnt
@@ -41,13 +15,3 @@ class ReRoCCTestConfig extends Config(
   new chipyard.config.WithAccumulatorRoCC ++                   // rerocc tile0 is accum
   new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
-
-class ReRoCCManyGemminiConfig extends Config(
-  new rerocc.WithReRoCC ++
-  new gemmini.LeanGemminiConfig ++                              // rerocc tile3 is gemmini
-  new gemmini.LeanGemminiConfig ++                              // rerocc tile2 is gemmini
-  new gemmini.LeanGemminiConfig ++                              // rerocc tile1 is gemmini
-  new gemmini.LeanGemminiConfig ++                              // rerocc tile0 is gemmini
-  new freechips.rocketchip.rocket.WithNHugeCores(4) ++           // 4 rocket cores
-  new chipyard.config.AbstractConfig)
-
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 0cdb612fe0..b0cea36c66 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -115,17 +115,6 @@ class SV48RocketConfig extends Config(
   new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
-// Rocket with Tacit encoder and trace sinks
-class TacitRocketConfig extends Config(
-  new tacit.WithTraceSinkDMA(1) ++
-  new tacit.WithTraceSinkAlways(0) ++
-  new chipyard.config.WithTraceArbiterMonitor ++
-  new chipyard.config.WithTacitEncoder ++
-  new chipyard.config.WithNPerfCounters(29) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
-  new chipyard.config.AbstractConfig)
-
 // Rocket with asynchronous reset for all domains **except for the Rocket Tile itself**.
 class AsyncResetRocketConfig extends Config(
   new chipyard.clocking.WithAsyncClockGroups("uncore") ++ // use async reset for the bus clock group
diff --git a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala
index 9253b61dbc..50dd4c1f48 100644
--- a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala
@@ -37,18 +37,3 @@ class dmiShuttleCosimConfig extends Config(
   new shuttle.common.WithShuttleDebugROB ++                      // enable shuttle debug ROB for cosim
   new shuttle.common.WithNShuttleCores ++
   new chipyard.config.AbstractConfig)
-
-class GemminiShuttleConfig extends Config(
-  new gemmini.DefaultGemminiConfig ++                            // use Gemmini systolic array GEMM accel
-  new shuttle.common.WithNShuttleCores ++
-  new chipyard.config.AbstractConfig)
-
-// Shuttle with Tacit encoder and trace sinks
-class TacitShuttleConfig extends Config(
-  new tacit.WithTraceSinkDMA(1) ++
-  new tacit.WithTraceSinkAlways(0) ++
-  new chipyard.config.WithTraceArbiterMonitor ++
-  new chipyard.config.WithTacitEncoder ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new shuttle.common.WithNShuttleCores ++
-  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
deleted file mode 100644
index f531fe0305..0000000000
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ /dev/null
@@ -1,59 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import org.chipsalliance.cde.config.{Config}
-
-class Sodor1StageConfig extends Config(
-  // Create a Sodor 1-stage core
-  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
-  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
-  new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new chipyard.config.AbstractConfig)
-
-class Sodor2StageConfig extends Config(
-  // Create a Sodor 2-stage core
-  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
-  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
-  new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new chipyard.config.AbstractConfig)
-
-class Sodor3StageConfig extends Config(
-  // Create a Sodor 1-stage core with two ports
-  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
-  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
-  new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new chipyard.config.AbstractConfig)
-
-class Sodor3StageSinglePortConfig extends Config(
-  // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
-  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
-  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
-  new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new chipyard.config.AbstractConfig)
-
-class Sodor5StageConfig extends Config(
-  // Create a Sodor 5-stage core
-  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
-  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
-  new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new chipyard.config.AbstractConfig)
-
-class SodorUCodeConfig extends Config(
-  // Construct a Sodor microcode-based single-bus core
-  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
-  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
-  new testchipip.serdes.WithSerialTLWidth(32) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
index c5d28919e6..4785d6cd21 100644
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -84,7 +84,6 @@ class TutorialNoCConfig extends Config(
   new chipyard.example.WithGCD ++
   new chipyard.harness.WithLoopbackNIC ++
   new icenet.WithIceNIC ++
-  new fftgenerator.WithFFTGenerator(numPoints=8) ++
   new chipyard.example.WithStreamingFIR ++
   new chipyard.example.WithStreamingPassthrough ++
 
diff --git a/generators/chipyard/src/main/scala/config/VexiiRiscvConfigs.scala b/generators/chipyard/src/main/scala/config/VexiiRiscvConfigs.scala
deleted file mode 100644
index 8effede25e..0000000000
--- a/generators/chipyard/src/main/scala/config/VexiiRiscvConfigs.scala
+++ /dev/null
@@ -1,13 +0,0 @@
-package chipyard
-
-import chisel3._
-
-import org.chipsalliance.cde.config.{Config}
-
-// ---------------------
-// VexiiRiscv Configs
-// ---------------------
-
-class VexiiRiscvConfig extends Config(
-  new vexiiriscv.WithNVexiiRiscvCores(1) ++
-  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
index c29b05d381..01064fcd90 100644
--- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
@@ -6,7 +6,6 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.diplomacy._
 
-import gemmini._
 
 import chipyard.{TestSuitesKey, TestSuiteHelper}
 
@@ -33,17 +32,6 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) =>
   }
 })
 
-class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data](
-  harts: Int*)(gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig) extends Config((site, here, up) => {
-  case MultiRoCCKey => up(MultiRoCCKey, site) ++ harts.distinct.map { i =>
-    (i -> Seq((p: Parameters) => {
-      implicit val q = p
-      val gemmini = LazyModule(new Gemmini(gemminiConfig))
-      gemmini
-    }))
-  }
-})
-
 class WithAccumulatorRoCC(op: OpcodeSet = OpcodeSet.custom1) extends Config((site, here, up) => {
   case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => {
     val accumulator = LazyModule(new AccumulatorExample(op, n = 4)(p))
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index 2e5d91eb57..da36e52bbe 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -8,16 +8,47 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
 import freechips.rocketchip.diplomacy._
 
-import cva6.{CVA6TileAttachParams}
-import sodor.common.{SodorTileAttachParams}
-import ibex.{IbexTileAttachParams}
-import vexiiriscv.{VexiiRiscvTileAttachParams}
 import testchipip.cosim.{TracePortKey, TracePortParams}
 import barf.{TilePrefetchingMasterPortParams}
 import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams}
-import tacit.{TacitEncoder, TacitBPParams}
 import shuttle.common.{ShuttleTileAttachParams}
 
+// Static plugin discovery for optional generators via Java ServiceLoader.
+// Optional generators can implement TilePluginProvider.
+import scala.jdk.CollectionConverters._
+import org.reflections.Reflections
+import freechips.rocketchip.subsystem.HierarchicalElementPortParamsLike
+
+trait TilePluginProvider {
+  def tileTraceEnableInjectors: Seq[PartialFunction[Any, Any]] = Nil
+  def tileTraceDisableInjectors: Seq[PartialFunction[Any, Any]] = Nil
+  def tilePrefetchInjectors(make: (Int, HierarchicalElementPortParamsLike) => HierarchicalElementPortParamsLike): Seq[PartialFunction[Any, Any]] = Nil
+}
+
+private object TilePlugins {
+  private lazy val providers: Seq[TilePluginProvider] = {
+    val reflections = new Reflections("chipyard")
+    val subs = reflections.getSubTypesOf(classOf[TilePluginProvider]).asScala.toSeq.distinct
+    subs.flatMap { cls =>
+      try Some(cls.getDeclaredConstructor().newInstance())
+      catch { case _: Throwable => None }
+    }
+  }
+
+  def traceEnableInjectors: Seq[PartialFunction[Any, Any]] =
+    providers.flatMap(_.tileTraceEnableInjectors)
+  def traceDisableInjectors: Seq[PartialFunction[Any, Any]] =
+    providers.flatMap(_.tileTraceDisableInjectors)
+  def prefetchInjectors(make: (Int, HierarchicalElementPortParamsLike) => HierarchicalElementPortParamsLike): Seq[PartialFunction[Any, Any]] =
+    providers.flatMap(_.tilePrefetchInjectors(make))
+
+  def applyInjectors[A](tp: A, injectors: Seq[PartialFunction[Any, Any]]): A = {
+    var acc: Any = tp
+    injectors.foreach { pf => if (pf.isDefinedAt(acc)) acc = pf(acc) }
+    acc.asInstanceOf[A]
+  }
+}
+
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -31,27 +62,29 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
 })
 
 class WithTraceIO extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(trace = true)))
-    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(trace = true)))
-    case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      trace = true))
-    case other => other
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { tp =>
+    val updated = tp match {
+      case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+        core = tp.tileParams.core.copy(trace = true)))
+      case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+        core = tp.tileParams.core.copy(trace = true)))
+      case other => other
+    }
+    TilePlugins.applyInjectors(updated, TilePlugins.traceEnableInjectors)
   }
   case TracePortKey => Some(TracePortParams())
 })
 
 class WithNoTraceIO extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(trace = false)))
-    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      core = tp.tileParams.core.copy(trace = false)))
-    case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      trace = false))
-    case other => other
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { tp =>
+    val updated = tp match {
+      case tp: boom.v3.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+        core = tp.tileParams.core.copy(trace = false)))
+      case tp: boom.v4.common.BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+        core = tp.tileParams.core.copy(trace = false)))
+      case other => other
+    }
+    TilePlugins.applyInjectors(updated, TilePlugins.traceDisableInjectors)
   }
   case TracePortKey => None
 })
@@ -68,40 +101,6 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
   }
 })
 
-// Add a Tacit encoder to each tile
-class WithTacitEncoder extends Config((site, here, up) => {
-   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      traceParams = Some(TraceEncoderParams(
-        encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
-        buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams(
-          nGroups = 1,
-          xlen = tp.tileParams.core.xLen,
-          iaddrWidth = tp.tileParams.core.xLen
-        ), 
-        bufferDepth = 16, 
-        coreStages = 5, 
-        bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
-        useArbiterMonitor = false
-      )),
-      core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
-    case tp: ShuttleTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      traceParams = Some(TraceEncoderParams(
-        encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
-        buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams(
-          nGroups = tp.tileParams.core.retireWidth,
-          xlen = tp.tileParams.core.xLen,
-          iaddrWidth = tp.tileParams.core.xLen
-        ), 
-        bufferDepth = 16, 
-        coreStages = 7, 
-        bpParams = TacitBPParams(xlen = tp.tileParams.core.xLen, n_entries = 1024))(p)),
-        useArbiterMonitor = false
-      )),
-      core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
-   }
- })
-
 // Add a monitor to RTL print the sinked packets into a file for debugging
 class WithTraceArbiterMonitor extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -144,21 +143,19 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
 })
 
 class WithTilePrefetchers extends Config((site, here, up) => {
-  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
-    case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: VexiiRiscvTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
-    case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
-      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { tp =>
+    val updated = tp match {
+      case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+        master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
+      case tp: boom.v3.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+        master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
+      case tp: boom.v4.common.BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
+        master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
+      case other => other
+    }
+    val make = (tileId: Int, master: HierarchicalElementPortParamsLike) =>
+      barf.TilePrefetchingMasterPortParams(tileId, master)
+    TilePlugins.applyInjectors(updated, TilePlugins.prefetchInjectors(make))
   }
 })
 
diff --git a/generators/cva6 b/generators/cva6
index 17e9b5119f..187ed3cd12 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 17e9b5119f2e7021f1bce67f2601dedc5bfecc5c
+Subproject commit 187ed3cd126c68659f446c963599525c2bf58420
diff --git a/generators/fft-generator b/generators/fft-generator
index dde437e358..9146db738e 160000
--- a/generators/fft-generator
+++ b/generators/fft-generator
@@ -1 +1 @@
-Subproject commit dde437e3585328478e64a9be10635f051e40f635
+Subproject commit 9146db738e8fe39afbaf3bbdcc6375725e255268
diff --git a/generators/gemmini b/generators/gemmini
index 7a7e0e17d8..6ad65b90b1 160000
--- a/generators/gemmini
+++ b/generators/gemmini
@@ -1 +1 @@
-Subproject commit 7a7e0e17d80669d7d32561a3ffc9721e943333af
+Subproject commit 6ad65b90b1eb270c20ce4f04109e3dde0180b36f
diff --git a/generators/ibex b/generators/ibex
index 1800a1bf9f..5129576841 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 1800a1bf9f4ef5b4bf396e4bd1fdc36117c2a7a5
+Subproject commit 5129576841529ee5581e038e0678de972baf1e76
diff --git a/generators/nvdla b/generators/nvdla
index 768abfbcd6..33d87f5600 160000
--- a/generators/nvdla
+++ b/generators/nvdla
@@ -1 +1 @@
-Subproject commit 768abfbcd6f1cab97eaca802d5841faeb46a1d92
+Subproject commit 33d87f56004763b503c60931b8a37f7bff3a17ff
diff --git a/generators/radiance b/generators/radiance
index b4310b2077..6da03014f0 160000
--- a/generators/radiance
+++ b/generators/radiance
@@ -1 +1 @@
-Subproject commit b4310b2077ca9f4676b1ae7405efa69501ad631d
+Subproject commit 6da03014f045a58626214234c10023a2ccf0e295
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index 32d49f96dd..910a2e83ce 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit 32d49f96dd9ff37ff7fb2eab875a285f6e4dc295
+Subproject commit 910a2e83ce206e86372927ec3e0b8056953f7d95
diff --git a/generators/tacit b/generators/tacit
index d188bb073b..fe61365292 160000
--- a/generators/tacit
+++ b/generators/tacit
@@ -1 +1 @@
-Subproject commit d188bb073b7d31f3f649d8fb640c43091c90dae6
+Subproject commit fe61365292ef1fa60410a2a91c48a3e3d22b1a75
diff --git a/generators/vexiiriscv b/generators/vexiiriscv
index 10a351329e..c82fcfcd5c 160000
--- a/generators/vexiiriscv
+++ b/generators/vexiiriscv
@@ -1 +1 @@
-Subproject commit 10a351329eb2f8b0ebf29331e0fe911fe3bb5a9b
+Subproject commit c82fcfcd5cad4a416987ed12aef75b45a7892b5c
diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh
index 22959d1a53..a3111e5066 100755
--- a/scripts/init-submodules-no-riscv-tools-nolog.sh
+++ b/scripts/init-submodules-no-riscv-tools-nolog.sh
@@ -40,6 +40,15 @@ function usage
     echo "  --compressacc Initialize the optional compressor accelerator submodule"
     echo "  --mempress    Initialize the optional mempress accelerator submodule"
     echo "  --saturn      Initialize the optional saturn vector-unit submodule"
+    echo "  --fft         Initialize the optional FFT accelerator submodule"
+    echo "  --radiance    Initialize the optional Radiance accelerator submodule"
+    echo "  --gemmini     Initialize the optional Gemmini accelerator submodule"
+    echo "  --nvdla       Initialize the optional NVDLA accelerator submodule"
+    echo "  --cva6        Initialize the optional CVA6 core submodule"
+    echo "  --sodor       Initialize the optional Sodor cores submodule"
+    echo "  --ibex        Initialize the optional Ibex core submodule"
+    echo "  --vexiiriscv  Initialize the optional VexiiRiscv core submodule"
+    echo "  --tacit       Initialize the optional Tacit trace encoder submodule"
     echo ""
 }
 
@@ -48,6 +57,15 @@ ENABLE_CALIPTRA=0
 ENABLE_COMPRESSACC=0
 ENABLE_MEMPRESS=0
 ENABLE_SATURN=0
+ENABLE_FFT=0
+ENABLE_RADIANCE=0
+ENABLE_GEMMINI=0
+ENABLE_NVDLA=0
+ENABLE_CVA6=0
+ENABLE_SODOR=0
+ENABLE_IBEX=0
+ENABLE_VEXIIRISCV=0
+ENABLE_TACIT=0
 
 while test $# -gt 0
 do
@@ -58,12 +76,21 @@ do
             ;;
         --force | -f | --skip-validate) # Deprecated flags
             ;;
-	--full)
+    	--full)
 	    ENABLE_ARA=1
 	    ENABLE_CALIPTRA=1
 	    ENABLE_COMPRESSACC=1
 	    ENABLE_MEMPRESS=1
 	    ENABLE_SATURN=1
+            ENABLE_CVA6=1
+            ENABLE_SODOR=1
+	    ENABLE_IBEX=1
+    	    ENABLE_VEXIIRISCV=1
+            ENABLE_FFT=1
+            ENABLE_RADIANCE=1
+            ENABLE_GEMMINI=1
+            ENABLE_NVDLA=1
+            ENABLE_TACIT=1
 	    ;;
 	--ara)
 	    ENABLE_ARA=1
@@ -80,6 +107,33 @@ do
 	--saturn)
 	    ENABLE_SATURN=1
 	    ;;
+	--fft)
+	    ENABLE_FFT=1
+	    ;;
+	--radiance)
+	    ENABLE_RADIANCE=1
+	    ;;
+	--gemmini)
+	    ENABLE_GEMMINI=1
+	    ;;
+	--nvdla)
+	    ENABLE_NVDLA=1
+	    ;;
+	--cva6)
+	    ENABLE_CVA6=1
+	    ;;
+    	--sodor)
+    	    ENABLE_SODOR=1
+    	    ;;
+    	--ibex)
+    	    ENABLE_IBEX=1
+    	    ;;
+    	--vexiiriscv)
+    	    ENABLE_VEXIIRISCV=1
+    	    ;;
+    	--tacit)
+    	    ENABLE_TACIT=1
+    	    ;;
         *)
             echo "ERROR: bad argument $1"
             usage
@@ -126,16 +180,20 @@ cd "$RDIR"
             toolchains/*-tools/* \
 	    toolchains/libgloss \
 	    generators/cva6 \
+            generators/ibex \
+            generators/riscv-sodor \
+            generators/vexiiriscv \
             generators/ara \
 	    generators/caliptra-aes-acc \
 	    generators/compress-acc \
             generators/nvdla \
 	    generators/mempress \
             generators/gemmini \
+            generators/fft-generator \
+            generators/radiance \
             generators/rocket-chip \
 	    generators/saturn \
-            generators/compress-acc \
-            generators/vexiiriscv \
+            generators/tacit \
             sims/firesim \
             software/nvdla-workload \
             software/coremark \
@@ -163,24 +221,25 @@ cd "$RDIR"
 )
 
 (
-    # Non-recursive clone to exclude cva6 submods
-    submodule_name="generators/cva6"
-    git submodule update --init generators/cva6 || exit 1
-    git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6 || exit 1
-    git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi || exit 1
-    git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi_riscv_atomics || exit 1
-    git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/common_cells || exit 1
-    git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/fpga-support || exit 1
-    git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/riscv-dbg || exit 1
-    git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/register_interface || exit 1
-    git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init --recursive src/fpu || exit 1
-    
-    # Non-recursive clone to exclude nvdla submods
-    submodule_name="generators/nvdla"
-    git submodule update --init generators/nvdla || exit 1
-    git -C generators/nvdla submodule update --init src/main/resources/hw || exit 1
-
-    # Optional clones
+    if [[ "$ENABLE_CVA6" -eq 1 ]] ; then
+        submodule_name="generators/cva6"
+        git submodule update --init generators/cva6 || exit 1
+        git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6 || exit 1
+        git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi || exit 1
+        git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi_riscv_atomics || exit 1
+        git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/common_cells || exit 1
+        git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/fpga-support || exit 1
+        git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/riscv-dbg || exit 1
+        git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/register_interface || exit 1
+        git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init --recursive src/fpu || exit 1
+    fi
+
+    if [[ "$ENABLE_NVDLA" -eq 1 ]] ; then
+        submodule_name="generators/nvdla"
+        git submodule update --init generators/nvdla || exit 1
+        git -C generators/nvdla submodule update --init src/main/resources/hw || exit 1
+    fi
+
     if [[ "$ENABLE_ARA" -eq 1 ]] ; then
 	git submodule update --init generators/ara || exit 1
 	git -C generators/ara submodule update --init ara || exit 1
@@ -190,6 +249,14 @@ cd "$RDIR"
 	git submodule update --init generators/caliptra-aes-acc || exit 1
     fi
 
+    if [[ "$ENABLE_FFT" -eq 1 ]] ; then
+	git submodule update --init generators/fft-generator || exit 1
+    fi
+
+    if [[ "$ENABLE_RADIANCE" -eq 1 ]] ; then
+	git submodule update --init --recursive generators/radiance || exit 1
+    fi
+
     if [[ "$ENABLE_COMPRESSACC" -eq 1 ]] ; then
 	git submodule update --init generators/compress-acc || exit 1
     fi
@@ -201,23 +268,35 @@ cd "$RDIR"
     if [[ "$ENABLE_SATURN" -eq 1 ]] ; then
 	git submodule update --init --recursive generators/saturn || exit 1
     fi
-    
-    # Non-recursive clone to exclude gemmini-software
-    submodule_name="generators/gemmini"
-    git submodule update --init generators/gemmini || exit 1
-    git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests || exit 1
 
-    # Non-recursive clone
-    submodule_name="generators/rocket-chip"
-    git submodule update --init generators/rocket-chip || exit 1
+    if [[ "$ENABLE_SODOR" -eq 1 ]] ; then
+	git submodule update --init generators/riscv-sodor || exit 1
+    fi
+
+    if [[ "$ENABLE_IBEX" -eq 1 ]] ; then
+	git submodule update --init --recursive generators/ibex || exit 1
+    fi
 
+    if [[ "$ENABLE_VEXIIRISCV" -eq 1 ]] ; then
+	git submodule update --init generators/vexiiriscv || exit 1
+        git -C generators/vexiiriscv submodule update --init VexiiRiscv || exit 1
+        git -C generators/vexiiriscv/VexiiRiscv submodule update --init ext/SpinalHDL || exit 1
+        git -C generators/vexiiriscv/VexiiRiscv submodule update --init ext/rvls || exit 1
+    fi
+
+    if [[ "$ENABLE_TACIT" -eq 1 ]] ; then
+	git submodule update --init generators/tacit || exit 1
+    fi
+
+    if [[ "$ENABLE_GEMMINI" -eq 1 ]] ; then
+        submodule_name="generators/gemmini"
+        git submodule update --init generators/gemmini || exit 1
+        git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests || exit 1
+    fi
 
     # Non-recursive clone
-    submodule_name="generators/vexiiriscv"
-    git submodule update --init generators/vexiiriscv || exit 1
-    git -C generators/vexiiriscv submodule update --init VexiiRiscv || exit 1
-    git -C generators/vexiiriscv/VexiiRiscv submodule update --init ext/SpinalHDL || exit 1
-    git -C generators/vexiiriscv/VexiiRiscv submodule update --init ext/rvls || exit 1
+    submodule_name="generators/rocket-chip"
+    git submodule update --init generators/rocket-chip || exit 1
 
     # Minimal non-recursive clone to initialize sbt dependencies
     submodule_name="sims/firesim"