Hammer hierarchical pitch checks

[jwright6323]

Documenting a discussion @colinschmidt and I had in the work session about hierarchical pitch checks. This depends on #112 so I will bump the priority up there accordingly.

There are two types of hierarchical cells we care about: Tiled cells (more broadly: MIM cells), and single-instance cells (1 of each on the chip).

Rule 1a.w and 1a.h: Single-instance cells should check that width and height are integer multiples of the std cell grid width and height, respectively.

Rule 1b: Single-instance cells should check that the origin is on the std cell grid.

Rule 2a.w: Tiled cells should check that the width is an integer multiple of the LCM of the following values:

• standard cell x
• all vertical routing pitches of layers used as pins
• all vertical power strap group pitches of layers intended to abut at the top level

Rule 2a.h: Tiled cells should check that the width is an integer multiple of the LCM of the following values:

• standard cell y
• all horizontal routing pitches of layers used as pins
• all horizontal power strap group pitches of layers intended to abut at the top level

Rule 2b: Tiled cells should check that the origin is on the std cell grid.

Rule 2c: Tiled cells need to be on the bump pitch if they interface with bumps

...And there may be a few more.

[jwright6323]

Other hierarchical checks:

• (related to Hierarchical constraints not propagated correctly in certain circumstances #401) if using a hierarchical flow, top-level bump placements should be an error- we should force them to be placed inside the hierarchical constraints list