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Merge pull request #81 from ucb-ucie/e2e_integraion
E2e integration of the UCIe stack
2 parents 2388f0d + 69989cf commit 1a31e02

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-66
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10 files changed

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-66
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‎src/main/scala/e2e/UCITop.scala‎

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,84 @@
1+
package edu.berkeley.cs.ucie.digital
2+
package e2e
3+
4+
import chisel3._
5+
import chisel3.util._
6+
7+
import interfaces._
8+
import sideband._
9+
import protocol._
10+
import d2dadapter._
11+
import logphy._
12+
import freechips.rocketchip.util.AsyncQueueParams
13+
14+
/**
15+
* UCITop is the main class which instantiates all the three
16+
* layers of the UCIe protocol stack
17+
*
18+
*/
19+
class UCITop(val fdiParams: FdiParams, val rdiParams: RdiParams,
20+
val sbParams: SidebandParams, val myId: BigInt,
21+
val linkTrainingParams: LinkTrainingParams,
22+
val afeParams: AfeParams,
23+
val laneAsyncQueueParams: AsyncQueueParams) extends Module {
24+
val io = IO(new Bundle{
25+
// IOs for connecting to the protocol layer
26+
//val fdi = new Fdi(fdiParams)
27+
val fdi_lpConfig = Valid(Bits(fdiParams.sbWidth.W))
28+
val fdi_lpConfigCredit = Input(Bool())
29+
val fdi_plConfig = Flipped(Valid(Bits(fdiParams.sbWidth.W)))
30+
val fdi_plConfigCredit = Output(Bool())
31+
val fdi_lpStallAck = Output(Bool())
32+
val TLplStateStatus = Output(PhyState())
33+
34+
val TLlpData_valid = Input(Bool())
35+
val TLlpData_bits = Input(Bits((8 * fdiParams.width).W))
36+
val TLlpData_irdy = Input(Bool())
37+
val TLlpData_ready = Output(Bool())
38+
val TLplData_bits = Output(Bits((8 * fdiParams.width).W))
39+
val TLplData_valid = Output(Bool())
40+
val TLready_to_rcv = Input(Bool())
41+
val fault = Input(Bool())
42+
val soft_reset = Input(Bool())
43+
// IOs for connecting to the AFE
44+
val mbAfe = new MainbandAfeIo(afeParams)
45+
val sbAfe = new SidebandAfeIo(afeParams)
46+
})
47+
48+
// Instantiate the agnostic protocol layer
49+
val protocol = Module(new ProtocolLayer(fdiParams))
50+
// Instantiate the D2D adapter
51+
val d2dadapter = Module(new D2DAdapter(fdiParams, rdiParams, sbParams))
52+
// Instantiate the logPhy
53+
val logPhy = Module(new LogicalPhy(myId, linkTrainingParams, afeParams, rdiParams, fdiParams, sbParams, laneAsyncQueueParams))
54+
55+
// Connect the FDI interface of Protocol layer to D2D adapter
56+
protocol.io.fdi <> d2dadapter.io.fdi
57+
58+
// Connect the RDI interface of D2D adapter to logPhy
59+
d2dadapter.io.rdi <> logPhy.io.rdi
60+
61+
// Connect the AFE interface from logPhy to the top
62+
io.mbAfe <> logPhy.io.mbAfe
63+
io.sbAfe <> logPhy.io.sbAfe
64+
65+
// Connect the protocol IOs to the top for connections to the tilelink interface
66+
//io.fdi <> protocol.io.fdi
67+
io.fdi_lpConfig <> protocol.io.fdi.lpConfig
68+
io.fdi_lpConfigCredit <> protocol.io.fdi.lpConfigCredit
69+
io.fdi_plConfig <> protocol.io.fdi.plConfig
70+
io.fdi_plConfigCredit <> protocol.io.fdi.plConfigCredit
71+
io.fdi_lpStallAck <> protocol.io.fdi.lpStallAck
72+
io.TLplStateStatus <> protocol.io.TLplStateStatus
73+
74+
protocol.io.TLlpData_valid := io.TLlpData_valid
75+
protocol.io.TLlpData_bits := io.TLlpData_bits
76+
protocol.io.TLlpData_irdy := io.TLlpData_irdy
77+
io.TLlpData_ready := protocol.io.TLlpData_ready
78+
io.TLplData_bits := protocol.io.TLplData_bits
79+
io.TLplData_valid := protocol.io.TLplData_valid
80+
protocol.io.TLready_to_rcv := io.TLready_to_rcv
81+
protocol.io.fault := io.fault
82+
protocol.io.soft_reset := io.soft_reset
83+
84+
}

‎src/main/scala/protocol/ProtocolLayer.scala‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,19 +19,24 @@ import javax.swing.InputMap
1919
class ProtocolLayer(val fdiParams: FdiParams) extends Module {
2020
val io = IO(new Bundle{
2121
val fdi = new Fdi(fdiParams)
22+
val TLplStateStatus = Output(PhyState())
2223
val TLlpData_valid = Input(Bool())
2324
val TLlpData_bits = Input(Bits((8 * fdiParams.width).W))
2425
val TLlpData_irdy = Input(Bool())
26+
val TLlpData_ready = Output(Bool())
2527
val TLplData_bits = Output(Bits((8 * fdiParams.width).W))
2628
val TLplData_valid = Output(Bool())
2729
val TLready_to_rcv = Input(Bool())
2830
val fault = Input(Bool())
2931
val soft_reset = Input(Bool())
3032
})
3133

34+
io.TLplStateStatus := io.fdi.plStateStatus
35+
3236
io.fdi.lpData.bits := io.TLlpData_bits
3337
io.fdi.lpData.valid := io.TLlpData_valid
3438
io.fdi.lpData.irdy := io.TLlpData_irdy
39+
io.TLlpData_ready := io.fdi.lpData.ready
3540

3641
io.TLplData_valid := io.fdi.plData.valid
3742
io.TLplData_bits := io.fdi.plData.bits

‎src/main/scala/tilelink/Configs.scala‎

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,19 @@ import freechips.rocketchip.subsystem._
1212
import freechips.rocketchip.regmapper.{HasRegMap, RegField}
1313
import interfaces._
1414
import protocol._
15+
import sideband.{SidebandParams}
16+
import logphy.{LinkTrainingParams}
1517

1618
case class UCITLParams (
17-
val fdi: FdiParams,
18-
val proto: ProtocolLayerParams,
19-
val tl: TileLinkParams
19+
val protoParams: ProtocolLayerParams,
20+
val tlParams: TileLinkParams,
21+
val fdiParams: FdiParams,
22+
val rdiParams: RdiParams,
23+
val sbParams: SidebandParams,
24+
val myId: BigInt,
25+
val linkTrainingParams: LinkTrainingParams,
26+
val afeParams: AfeParams,
27+
val laneAsyncQueueParams: AsyncQueueParams
2028
)
2129

2230
case object UCITLKey extends Field[Option[UCITLParams]](None)
@@ -25,13 +33,19 @@ trait CanHaveTLUCIAdapter { this: BaseSubsystem =>
2533
p(UCITLKey).map { params =>
2634
val bus = locateTLBusWrapper(SBUS) //TODO: make parameterizable?
2735
val uciTL = LazyModule(new UCITLFront(
28-
tlParams = params.tl,
29-
protoParams = params.proto,
30-
fdiParams = params.fdi
36+
tlParams = params.tlParams,
37+
protoParams = params.protoParams,
38+
fdiParams = params.fdiParams,
39+
rdiParams = params.rdiParams,
40+
sbParams = params.sbParams,
41+
myId = params.myId,
42+
linkTrainingParams = params.linkTrainingParams,
43+
afeParams = params.afeParams,
44+
laneAsyncQueueParams = params.laneAsyncQueueParams
3145
))
3246
uciTL.clockNode := bus.fixedClockNode
3347
bus.coupleTo(s"ucie_tl_man_port") {
34-
uciTL.managerNode := TLWidthWidget(bus.beatBytes) := TLSourceShrinker(params.tl.sourceIDWidth) := TLFragmenter(bus.beatBytes, p(CacheBlockBytes)) := _
48+
uciTL.managerNode := TLWidthWidget(bus.beatBytes) := TLSourceShrinker(params.tlParams.sourceIDWidth) := TLFragmenter(bus.beatBytes, p(CacheBlockBytes)) := _
3549
} //manager node because SBUS is making request?
3650
bus.coupleFrom(s"ucie_tl_cl_port") { _ := TLWidthWidget(bus.beatBytes) := uciTL.clientNode }
3751
bus.coupleTo(s"ucie_tl_ctrl_port") { uciTL.regNode.node := TLWidthWidget(bus.beatBytes) := TLFragmenter(bus.beatBytes, bus.blockBytes) := _ }

‎src/main/scala/tilelink/UCITLFront.scala‎

Lines changed: 54 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,11 @@ import freechips.rocketchip.prci._
1111
import freechips.rocketchip.subsystem._
1212
import freechips.rocketchip.util._
1313

14+
import e2e._
1415
import protocol._
1516
import interfaces._
1617
import sideband._
18+
import logphy.{LinkTrainingParams}
1719

1820
// TODO: Sideband messaging
1921
/** Main class to generate manager, client and register nodes on the tilelink diplomacy.
@@ -22,7 +24,11 @@ import sideband._
2224
* an agnostic interface to generate FDI signalling.
2325
*/
2426
class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerParams,
25-
val fdiParams: FdiParams)
27+
val fdiParams: FdiParams, val rdiParams: RdiParams,
28+
val sbParams: SidebandParams, val myId: BigInt,
29+
val linkTrainingParams: LinkTrainingParams,
30+
val afeParams: AfeParams,
31+
val laneAsyncQueueParams: AsyncQueueParams)
2632
(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) {
2733

2834
val device = new SimpleDevice("ucie-front", Seq("ucie,ucie0"))
@@ -58,20 +64,28 @@ class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerPar
5864

5965
class UCITLFrontImp extends Impl {
6066
val io = IO(new Bundle {
61-
// val sbus_clk = Input(Clock()) // System bus clock
62-
// val sbus_reset = Input(Bool()) // System bus reset
63-
// val lclk = Input(Clock()) // lclk is the FDI signalling clock
64-
// val lreset = Input(Bool()) // should the UCIe modules have its own reset?
65-
val fdi = new Fdi(fdiParams)
67+
// FDI interface for testing purposes only
68+
//val fdi = new Fdi(fdiParams)
69+
// IOs for connecting to the AFE
70+
val mbAfe = new MainbandAfeIo(afeParams)
71+
val sbAfe = new SidebandAfeIo(afeParams)
6672
})
6773
withClockAndReset(clock, reset) {
6874

75+
withClockAndReset(clock, reset) {
76+
6977
val fault = RegInit(false.B) // if fault in ecc code
7078

7179
// Instantiate the agnostic protocol layer
72-
val protocol = Module(new ProtocolLayer(fdiParams))
73-
io.fdi <> protocol.io.fdi
74-
protocol.io.fault := fault
80+
//val protocol = Module(new ProtocolLayer(fdiParams))
81+
val ucietop = Module(new UCITop(fdiParams, rdiParams,
82+
sbParams, myId,
83+
linkTrainingParams,
84+
afeParams, laneAsyncQueueParams))
85+
//io.fdi <> ucietop.io.fdi
86+
ucietop.io.fault := fault
87+
io.mbAfe <> ucietop.io.mbAfe
88+
io.sbAfe <> ucietop.io.sbAfe
7589

7690
// Hamming encode and decode
7791
val hammingEncoder = Module(new HammingEncode(protoParams))
@@ -84,13 +98,13 @@ class UCITLFrontImp extends Impl {
8498
//Sideband node for protocol layer
8599
val protocol_sb_node = Module(new SidebandNode((new SidebandParams), fdiParams))
86100

87-
protocol_sb_node.io.outer.rx.bits := protocol.io.fdi.lpConfig.bits
88-
protocol_sb_node.io.outer.rx.valid := protocol.io.fdi.lpConfig.valid
89-
protocol.io.fdi.lpConfigCredit := protocol_sb_node.io.outer.rx.credit
101+
protocol_sb_node.io.outer.rx.bits := ucietop.io.fdi_lpConfig.bits
102+
protocol_sb_node.io.outer.rx.valid := ucietop.io.fdi_lpConfig.valid
103+
ucietop.io.fdi_lpConfigCredit := protocol_sb_node.io.outer.rx.credit
90104

91-
protocol.io.fdi.plConfig.bits := protocol_sb_node.io.outer.tx.bits
92-
protocol.io.fdi.plConfig.valid := protocol_sb_node.io.outer.tx.valid
93-
protocol_sb_node.io.outer.tx.credit := protocol.io.fdi.plConfigCredit
105+
ucietop.io.fdi_plConfig.bits := protocol_sb_node.io.outer.tx.bits
106+
ucietop.io.fdi_plConfig.valid := protocol_sb_node.io.outer.tx.valid
107+
protocol_sb_node.io.outer.tx.credit := ucietop.io.fdi_plConfigCredit
94108

95109
protocol_sb_node.io.inner.layer_to_node.bits := Cat(regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high,
96110
regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_low,
@@ -145,7 +159,7 @@ class UCITLFrontImp extends Impl {
145159
//val txTLPayload = Wire(new TLBundleAUnionD(tlParams))
146160

147161
val aHasData = manager_edge.hasData(manager_tl.a.bits)
148-
val rx_fire = protocol.io.TLplData_valid
162+
val rx_fire = ucietop.io.TLplData_valid
149163
val uciRxPayload = Wire(new UCIRawPayloadFormat(tlParams, protoParams)) // User-defined UCIe flit for streaming
150164
val uciTxPayload = Wire(new UCIRawPayloadFormat(tlParams, protoParams)) // User-defined UCIe flit for streaming
151165

@@ -156,15 +170,15 @@ class UCITLFrontImp extends Impl {
156170
txDTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))
157171

158172
/*
159-
manager_tl.a.ready = (inward.io.enq.ready & ~protocol.io.fdi.lpStallAck &
160-
(protocol.io.fdi.plStateStatus === PhyState.active))
173+
manager_tl.a.ready = (inward.io.enq.ready & ~ucietop.io.fdi_lpStallAck &
174+
(ucietop.io.TLplStateStatus === PhyState.active))
161175
inward.io.enq.valid := manager_tl.a.fire
162176
*/
163177

164178
// A request to partner die logic
165179
// enqueue on the A channel queue
166-
manager_tl.a.ready := (inwardA.io.enq.ready & ~protocol.io.fdi.lpStallAck &
167-
(protocol.io.fdi.plStateStatus === PhyState.active))
180+
manager_tl.a.ready := (inwardA.io.enq.ready & ~ucietop.io.fdi_lpStallAck &
181+
(ucietop.io.TLplStateStatus === PhyState.active))
168182
inwardA.io.enq.valid := manager_tl.a.fire
169183
inwardA.io.enq.bits <> manager_tl.a.bits
170184

@@ -176,8 +190,8 @@ class UCITLFrontImp extends Impl {
176190
creditedMsgA.io.credit.bits := uciRxPayload.cmd.tlACredit
177191

178192
// D response to partner die's A request logic
179-
client_tl.d.ready := (inwardD.io.enq.ready & ~protocol.io.fdi.lpStallAck &
180-
(protocol.io.fdi.plStateStatus === PhyState.active))
193+
client_tl.d.ready := (inwardD.io.enq.ready & ~ucietop.io.fdi_lpStallAck &
194+
(ucietop.io.TLplStateStatus === PhyState.active))
181195
inwardD.io.enq.valid := client_tl.d.fire
182196
inwardD.io.enq.bits <> client_tl.d.bits
183197

@@ -237,11 +251,11 @@ class UCITLFrontImp extends Impl {
237251
tx_pipe.io.enq.bits := uciTxPayload
238252
tx_pipe.io.enq.valid := txArbiter.io.out.fire
239253
// Dequeue the TX TL packets and translate to UCIe flit
240-
txArbiter.io.out.ready := protocol.io.fdi.lpData.ready // if pl_trdy is asserted
254+
txArbiter.io.out.ready := ucietop.io.TLlpData_ready // if pl_trdy is asserted
241255
// specs implies that these needs to be asserted at the same time
242-
protocol.io.TLlpData_valid := tx_pipe.io.deq.valid & (~protocol.io.fdi.lpStallAck)
243-
protocol.io.TLlpData_irdy := tx_pipe.io.deq.valid & (~protocol.io.fdi.lpStallAck)
244-
protocol.io.TLlpData_bits := Cat(tx_pipe.io.deq.bits.asUInt(511,64), checksum_reg.asUInt) // assign uciTXPayload to the FDI lp data signa
256+
ucietop.io.TLlpData_valid := tx_pipe.io.deq.valid & (~ucietop.io.fdi_lpStallAck)
257+
ucietop.io.TLlpData_irdy := tx_pipe.io.deq.valid & (~ucietop.io.fdi_lpStallAck)
258+
ucietop.io.TLlpData_bits := Cat(tx_pipe.io.deq.bits.asUInt(511,64), checksum_reg.asUInt) // assign uciTXPayload to the FDI lp data signa
245259

246260
val creditA = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLA)
247261
val creditB = (txArbiter.io.out.bits.msgType === UCIProtoMsgTypes.TLB)
@@ -302,26 +316,25 @@ class UCITLFrontImp extends Impl {
302316
// =======================
303317
val rxTLPayload = Wire(new TLBundleAUnionD(tlParams))
304318
rxTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))
305-
// protocol.io.fdi.lpData.irdy := outward.io.enq.ready
306-
319+
// ucietop.io.fdi_lpData.irdy := outward.io.enq.ready
307320
// map the uciRxPayload and the plData based on the uciPayload formatting
308321
// map the uciRxPayload to the rxTLPayload TLBundle
309322
when(rx_fire) {
310323
// ucie cmd
311-
uciRxPayload.cmd := protocol.io.TLplData_bits(511, 448).asTypeOf(new UCICmdFormat(protoParams))
324+
uciRxPayload.cmd := ucietop.io.TLplData_bits(511, 448).asTypeOf(new UCICmdFormat(protoParams))
312325
// ucie header 1
313-
uciRxPayload.header1 := protocol.io.TLplData_bits(447,384).asTypeOf(new UCIHeader1Format(tlParams))
326+
uciRxPayload.header1 := ucietop.io.TLplData_bits(447,384).asTypeOf(new UCIHeader1Format(tlParams))
314327
// ucie header 2
315-
uciRxPayload.header2 := protocol.io.TLplData_bits(383, 320).asTypeOf(new UCIHeader2Format(tlParams))
328+
uciRxPayload.header2 := ucietop.io.TLplData_bits(383, 320).asTypeOf(new UCIHeader2Format(tlParams))
316329
// ucie data payload
317-
uciRxPayload.data(3) := protocol.io.TLplData_bits(319,256)
318-
uciRxPayload.data(2) := protocol.io.TLplData_bits(255,192)
319-
uciRxPayload.data(1) := protocol.io.TLplData_bits(191,128)
320-
uciRxPayload.data(0) := protocol.io.TLplData_bits(127,64)
330+
uciRxPayload.data(3) := ucietop.io.TLplData_bits(319,256)
331+
uciRxPayload.data(2) := ucietop.io.TLplData_bits(255,192)
332+
uciRxPayload.data(1) := ucietop.io.TLplData_bits(191,128)
333+
uciRxPayload.data(0) := ucietop.io.TLplData_bits(127,64)
321334
// ucie ecc
322-
uciRxPayload.ecc := protocol.io.TLplData_bits(63,0)
323-
hammingDecoder.io.data := protocol.io.TLplData_bits(511,64)
324-
hammingDecoder.io.checksum := protocol.io.TLplData_bits(63,0)
335+
uciRxPayload.ecc := ucietop.io.TLplData_bits(63,0)
336+
hammingDecoder.io.data := ucietop.io.TLplData_bits(511,64)
337+
hammingDecoder.io.checksum := ucietop.io.TLplData_bits(63,0)
325338

326339
// map the uciRxPayload to the rxTLPayload
327340
rxTLPayload.address := uciRxPayload.header1.address
@@ -368,10 +381,10 @@ class UCITLFrontImp extends Impl {
368381
}
369382
// when the RX queues are ready to get data
370383
val TLready_to_rcv = outwardA.io.in.ready || outwardD.io.in.ready
371-
protocol.io.TLready_to_rcv := TLready_to_rcv
384+
ucietop.io.TLready_to_rcv := TLready_to_rcv
372385

373386
// soft resets: can be reset or flush and reset, in flush and reset, the packets are
374387
// sent out before triggering reset
375-
protocol.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset |
388+
ucietop.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset |
376389
regNode.module.io.d2d_csrs.d2d_flush_and_reset)
377-
}}}
390+
}}}}

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