fix compilation errors

Author: rohanku

build.sbt

@@ -63,6 +63,7 @@ libraryDependencies ++=
 resolvers ++= Resolver.sonatypeOssRepos("snapshots")
 resolvers ++= Resolver.sonatypeOssRepos("releases")
 resolvers += Resolver.mavenLocal
+resolvers += "Sonatype OSS Snapshots" at "https://oss.sonatype.org/service/local/repositories/snapshots/content"
 
 addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)
 

src/main/scala/tilelink/Configs.scala

@@ -1,15 +1,14 @@
 package edu.berkeley.cs.ucie.digital
 package tilelink
 
+
 import chisel3._
 import freechips.rocketchip.util._
 import chisel3.util._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.subsystem._
-import testchipip.soc.{OBUS}
-//import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
 import interfaces._
 import protocol._
@@ -25,14 +24,36 @@ case class UCITLParams(
     val linkTrainingParams: LinkTrainingParams,
     val afeParams: AfeParams,
     val laneAsyncQueueParams: AsyncQueueParams,
+    val onchipAddr: Option[BigInt] = None,
 )
 
+case class InwardAddressTranslator(blockRange : AddressSet, replicationBase : Option[BigInt] = None)(implicit p: Parameters) extends LazyModule {
+  val module_side = replicationBase.map { base =>
+    val baseRegion   = AddressSet(0, base-1)
+    val replicator   = LazyModule(new RegionReplicator(ReplicatedRegion(baseRegion, baseRegion.widen(base))))
+    val prefixSource = BundleBridgeSource[UInt](() => UInt(1.W))
+    replicator.prefix := prefixSource
+    InModuleBody { prefixSource.bundle := 0.U(1.W) } // prefix is unused for TL uncached, so this is ok
+    replicator.node
+  }.getOrElse { TLTempNode() }
+
+  // val bus_side = TLFilter(TLFilter.mSelectIntersect(blockRange))(p)
+  val bus_side = TLFilter(TLFilter.mSubtract(blockRange))(p)
+
+  // module_side := bus_side
+
+  def apply(node : TLNode) : TLNode = {
+    node := module_side := bus_side
+  }
+
+  lazy val module = new LazyModuleImp(this) {}
+}
+
 case object UCITLKey extends Field[Option[UCITLParams]](None)
 
 trait CanHaveTLUCIAdapter { this: BaseSubsystem =>
   val uciTL = p(UCITLKey) match {
     case Some(params) => {
-      val obus = locateTLBusWrapper(OBUS) // TODO: make parameterizable?
       val sbus = locateTLBusWrapper(SBUS)
       val uciTL = LazyModule(
         new UCITLFront(
@@ -49,9 +70,15 @@ trait CanHaveTLUCIAdapter { this: BaseSubsystem =>
       )
 
       uciTL.clockNode := sbus.fixedClockNode
-      obus.coupleTo(s"ucie_tl_man_port") {
-          uciTL.managerNode := TLWidthWidget(obus.beatBytes) := TLBuffer() := TLSourceShrinker(params.tlParams.sourceIDWidth) := TLFragmenter(obus.beatBytes, p(CacheBlockBytes)) := TLBuffer() := _
-      } //manager node because SBUS is making request?
+      val manager_addr = AddressSet(params.tlParams.ADDRESS, params.tlParams.ADDR_RANGE)
+
+      val translator = uciTL {
+        LazyModule(InwardAddressTranslator(manager_addr, params.onchipAddr)(p))
+      }
+
+      sbus.coupleTo(s"ucie_tl_man_port") {
+          translator(uciTL.managerNode) := TLWidthWidget(sbus.beatBytes) := TLBuffer() := TLSourceShrinker(params.tlParams.sourceIDWidth) := TLFragmenter(sbus.beatBytes, p(CacheBlockBytes)) := TLBuffer() := _
+      }
       sbus.coupleFrom(s"ucie_tl_cl_port") { _ := TLBuffer() := TLWidthWidget(sbus.beatBytes) := TLBuffer() := uciTL.clientNode }
       sbus.coupleTo(s"ucie_tl_ctrl_port") { uciTL.regNode.node := TLWidthWidget(sbus.beatBytes) := TLFragmenter(sbus.beatBytes, sbus.blockBytes) := TLBuffer() := _ }
       Some(uciTL)