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Merge pull request #19 from ucb-eecs151tapeout/ee198-20-tac-working
Fix instructional flow, add `IS_TOP_LEVEL` and allow tutorial=sky130-commercial
2 parents 4ccc2ea + cf03a0d commit b287169

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+194
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‎conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml‎

Lines changed: 11 additions & 11 deletions
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‎scripts/build-setup.sh‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,8 @@ if run_step "1"; then
190190
fi
191191
echo "Storing main conda environment in $CONDA_ENV_NAME"
192192

193-
conda-lock install --conda $(which conda) $CONDA_ENV_ARG $LOCKFILE &&
193+
# Changed this from $(which conda)
194+
conda-lock install --conda $CONDA_EXE $CONDA_ENV_ARG $LOCKFILE &&
194195
source $(conda info --base)/etc/profile.d/conda.sh &&
195196
conda activate $CONDA_ENV_NAME
196197
exit_if_last_command_failed

‎vlsi/Makefile‎

Lines changed: 26 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,8 @@ SMEMS_COMP ?= $(tech_dir)/sram-compiler.json
2828
SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
2929
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
3030

31+
IS_TOP_RUN ?= 1
32+
3133
ifdef USE_SRAM_COMPILER
3234
TOP_MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
3335
else
@@ -40,10 +42,15 @@ TOOLS_CONF ?= tools.yml
4042
CHIP_CONF ?= design-ofo.yml
4143
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(CHIP_CONF)
4244
PIN_MAP ?= pin-map-ofo.yml
43-
HAMMER_EXEC ?= ./hammer-driver
45+
ifeq ($(IS_TOP_RUN),1)
46+
HAMMER_EXEC ?= ./hammer-driver
47+
else
48+
HAMMER_EXEC ?= ./example-vlsi-sky130
49+
endif
50+
4451
# $(if $(filter $(tech_name),sky130),\
45-
# ./example-vlsi-sky130,\
46-
# ./example-vlsi)
52+
# ./example-vlsi-sky130,\
53+
# ./example-vlsi)
4754
VLSI_TOP ?= $(TOP)
4855
VLSI_MODEL_DUT_NAME ?= chiptop0
4956
# If overriding, this should be relative to $(vlsi_dir)
@@ -118,7 +125,13 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
118125
# synthesis input configuration
119126
#########################################################################################
120127
SYN_CONF = $(OBJ_DIR)/inputs.yml
121-
GENERATED_CONFS = $(SYN_CONF) $(IO_FILE_CONF)
128+
GENERATED_CONFS = $(SYN_CONF)
129+
130+
ifeq ($(IS_TOP_RUN),1)
131+
# only use ios if non commercial
132+
GENERATED_CONFS = $(SYN_CONF) $(IO_FILE_CONF)
133+
endif
134+
122135
ifeq ($(CUSTOM_VLOG), )
123136
GENERATED_CONFS += $(SRAM_CONF)
124137
endif
@@ -129,31 +142,31 @@ $(SYN_CONF): $(VLSI_RTL)
129142
echo " input_files:" >> $@
130143
for x in $$(cat $(VLSI_RTL)); do \
131144
echo ' - "'$$x'"' >> $@; \
132-
done
145+
done
133146
echo " input_files_meta: 'append'" >> $@
134147
echo "synthesis.inputs:" >> $@
135148
echo " top_module: $(VLSI_TOP)" >> $@
136149
echo " input_files:" >> $@
137150
for x in $$(cat $(VLSI_RTL)); do \
138151
echo ' - "'$$x'"' >> $@; \
139-
done
152+
done
140153

141154
#########################################################################################
142155
# simulation and power input configuration
143156
#########################################################################################
144157
include $(base_dir)/sims/vcs/vcs.mk
145158

146159
SIM_FILE_REQS += \
147-
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
160+
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
148161

149162
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
150163
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(build_dir)
151164
cp -f $(SIM_FILE_REQS) $(build_dir)
152165
$(foreach file,\
153166
$(SIM_FILE_REQS),\
154167
$(if $(filter %.h,$(file)),\
155-
,\
156-
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
168+
,\
169+
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
157170

158171
include $(vlsi_dir)/sim.mk
159172

@@ -179,10 +192,10 @@ $(IO_FILE_CONF): $(IO_FILE)
179192

180193
.PHONY: buildfile
181194
buildfile: $(OBJ_DIR)/hammer.d
182-
# Tip: Set HAMMER_D_DEPS to an empty string to avoid unnecessary RTL rebuilds
183-
# TODO: make this dependency smarter so that we don't need this at all
184-
HAMMER_D_DEPS ?= $(GENERATED_CONFS)
185-
$(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
195+
# Tip: Set HAMMER_D_DEPS to an empty string to avoid unnecessary RTL rebuilds
196+
# TODO: make this dependency smarter so that we don't need this at all
197+
HAMMER_D_DEPS ?= $(GENERATED_CONFS)
198+
$(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
186199
$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build
187200

188201
-include $(OBJ_DIR)/hammer.d

‎vlsi/design-ofo.yml‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -183,50 +183,50 @@ design.def.hv_routing: ofo-hv-routing.def
183183
# Library stuff
184184
.local.library.sky130_fd_sc_hvl__lsbufhv2lv: &lib__sky130_fd_sc_hvl__lsbufhv2lv
185185
# gds_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_sc_hvl/gds/sky130_fd_sc_hvl.gds
186-
gds_file: /tools/commercial/skywater/skywater-pdk/libraries/sky130_fd_sc_hvl/latest/cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv_1.gds
186+
gds_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_fd_sc_hvl__lsbufhv2lv_1.gds
187187
lef_file: cache/fd_sc_hvl__lef/sky130_fd_sc_hvl__lsbufhv2lv_1.lef
188-
spice_file: /tools/C/rahulkumar/sky130/io_lvs/sky130_fd_sc_hvl.cdl
188+
spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_fd_sc_hvl.cdl
189189
# spice_file: /tools/C/nayiri/sky130/chipyard-jun23_tapeout/vlsi/sky130_fd_sc_hvl.cdl
190190
verilog_sim: ${technology.sky130.sky130A}/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl__lsbufhv2lv.functional.v
191191
provides:
192192
- lib_type: lvlshift
193193
vt: RVT
194-
.local.library.MultiPLLTop: &lib__MultiPLLTop
195-
# gds_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_sc_hvl/gds/sky130_fd_sc_hvl.gds
196-
gds_file: /tools/C/sehuang/sky130/jun23/jun23_pll_handoff/gds/MutliPLLTop_clean_6_2_0156.gds
197-
lef_file: /tools/C/sehuang/sky130/jun23/jun23_pll_handoff/lef/MultiPLLTop.lef
198-
spice_file: /tools/C/sehuang/sky130/jun23/jun23_pll_handoff/spice/MultiPLLTop.lvs.sp
199-
# TODO: verilog sim
200-
provides:
201-
- lib_type: block
202-
vt: RVT
194+
# .local.library.MultiPLLTop: &lib__MultiPLLTop
195+
# # gds_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_sc_hvl/gds/sky130_fd_sc_hvl.gds
196+
# gds_file: /tools/C/sehuang/sky130/jun23/jun23_pll_handoff/gds/MutliPLLTop_clean_6_2_0156.gds
197+
# lef_file: /tools/C/sehuang/sky130/jun23/jun23_pll_handoff/lef/MultiPLLTop.lef
198+
# spice_file: /tools/C/sehuang/sky130/jun23/jun23_pll_handoff/spice/MultiPLLTop.lvs.sp
199+
# # TODO: verilog sim
200+
# provides:
201+
# - lib_type: block
202+
# vt: RVT
203203

204204
vlsi.technology.manually_override_pdk_collateral: true
205205
vlsi.technology.override_libraries_meta: ["append", "lazydeepsubst"]
206206
vlsi.technology.override_libraries:
207207
- library:
208-
spice_file: /tools/C/rahulkumar/sky130/io_lvs/sky130_fd_io.spice
208+
spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_fd_io.spice
209209
- library:
210-
gds_file: ["/tools/C/rohankumar/sky130/stac_tapeout/gds/sky130_ef_io_with_overlay.gds", "sky130_ef_io.gds"]
210+
gds_file: ["/home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_ef_io_with_overlay.gds", "sky130_ef_io.gds"]
211211
# this is hacked in sky130/__init__.py
212212
#lef_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef
213-
spice_file: /tools/C/rahulkumar/sky130/io_lvs/sky130_ef_io.spice
213+
spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_ef_io.spice
214214
- library:
215-
spice_file: /tools/C/rahulkumar/sky130/stac2/lvs/sky130_fd_sc_hd.cdl
215+
spice_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_fd_sc_hd.cdl
216216
vlsi.technology.extra_libraries_meta: ["append", "lazydeepsubst"]
217217
vlsi.technology.extra_libraries:
218+
# - library:
219+
# gds_file: /bwrcq/C/elamdf/sky130/virtuoso_workdir/FILL16.gds
220+
# - library:
221+
# gds_file: /bwrcq/C/elamdf/sky130/virtuoso_workdir/FILL4.gds
222+
# - library:
223+
# gds_file: /bwrcq/C/elamdf/sky130/virtuoso_workdir/FILL1.gds
218224
- library:
219-
gds_file: /bwrcq/C/elamdf/sky130/virtuoso_workdir/FILL16.gds
220-
- library:
221-
gds_file: /bwrcq/C/elamdf/sky130/virtuoso_workdir/FILL4.gds
222-
- library:
223-
gds_file: /bwrcq/C/elamdf/sky130/virtuoso_workdir/FILL1.gds
224-
- library:
225-
spice_file: /tools/C/rahulkumar/sky130/stac2/lvs/devices.sp
225+
spice_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/devices.sp
226226
- library: # TODO: why is this required? seems like it isn't used in stacv2 repo
227227
spice_file: ${technology.sky130.sram22_sky130_macros}/sram22.spice
228228
- library:
229-
spice_file: /tools/C/rahulkumar/sky130/io_lvs/sky130_fd_io.spice
229+
spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_fd_io.spice
230230
- library:
231231
<<: *lib__sky130_fd_sc_hvl__lsbufhv2lv
232232
nldm_liberty_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_100C_1v65_lv1v60.lib
@@ -258,19 +258,19 @@ vlsi.technology.extra_libraries:
258258
VDD: "1.80 V"
259259
GND: "0 V"
260260
- library:
261-
gds_file: /tools/C/rohankumar/sky130/stac_tapeout/gds/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_and_vssio_vssa_vssd_slice_20um.gds
262-
lef_file: /tools/C/rohankumar/sky130/stac_tapeout/gds/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_and_vssio_vssa_vssd_slice_20um.lef
263-
spice_file: /tools/C/rahulkumar/sky130/io_lvs/sky130_ef_io.spice
261+
gds_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_and_vssio_vssa_vssd_slice_20um.gds
262+
lef_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_ef_io__connect_vcchib_vccd_and_vswitch_vddio_and_vssio_vssa_vssd_slice_20um.lef
263+
spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_ef_io.spice
264264
- library:
265-
spice_file: /tools/C/rahulkumar/sky130/io_lvs/sky130_ef_io__analog_pad_esd2.cdl
266-
gds_file: /tools/C/rohankumar/sky130/stac_tapeout/gds/sky130_ef_io__analog_pad_esd2.gds
267-
lef_file: /tools/C/rohankumar/sky130/stac_tapeout/sky130_ef_io__analog_pad_esd2.lef
265+
spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_ef_io__analog_pad_esd2.cdl
266+
gds_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_ef_io__analog_pad_esd2.gds
267+
lef_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_ef_io__analog_pad_esd2.lef
268268
provides:
269269
- lib_type: iocell
270270
- library:
271271
gds_file: ${technology.sky130.caravel}/gds/simple_por.gds
272272
lef_file: ${technology.sky130.caravel}/lef/simple_por.lef
273-
spice_file: /tools/C/rahulkumar/sky130/io_lvs/sky130_ef_io.spice
273+
spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_ef_io.spice
274274
verilog_sim: ${technology.sky130.caravel}/verilog/rtl/simple_por.v
275275
provides:
276276
- lib_type: por

‎vlsi/example-designs/sky130-commercial.yml‎

Lines changed: 31 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -24,36 +24,39 @@ vlsi.inputs.placement_constraints:
2424
x: 0
2525
y: 0
2626
width: 4000
27-
height: 3000
27+
height: 6000
2828
margins:
2929
left: 10
3030
right: 0
3131
top: 10
3232
bottom: 10
33-
# Place SRAM memory instances
34-
# data cache
35-
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_1/rockettile_dcache_data_arrays_0_ext/mem_0_0"
36-
37-
type: hardmacro
38-
x: 100
39-
y: 100
40-
orientation: r90
41-
#- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_0/rockettile_dcache_data_arrays_0_ext/mem_0_0"
42-
#type: hardmacro
43-
#x: 50
44-
#y: 800
45-
#orientation: r90
46-
47-
# tag array
48-
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_tag_array_0/rockettile_icache_tag_array_0_ext/mem_0_0"
49-
type: hardmacro
50-
x: 50
51-
y: 1600
52-
orientation: r90
53-
54-
# instruction cache
55-
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_data_arrays_0_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0"
56-
type: hardmacro
57-
x: 50
58-
y: 2100
59-
orientation: r90
33+
# # Place SRAM memory instances
34+
# # data cache
35+
# - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_1/rockettile_dcache_data_arrays_0_ext/mem_0_0"
36+
#
37+
# type: hardmacro
38+
# x: 100
39+
# y: 100
40+
# orientation: r90
41+
# #- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/rockettile_dcache_data_arrays_0/rockettile_dcache_data_arrays_0_ext/mem_0_0"
42+
# #type: hardmacro
43+
# #x: 50
44+
# #y: 800
45+
# #orientation: r90
46+
#
47+
# # tag array
48+
# - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_tag_array_0/rockettile_icache_tag_array_0_ext/mem_0_0"
49+
# type: hardmacro
50+
# x: 50
51+
# y: 1600
52+
# orientation: r90
53+
#
54+
# # instruction cache
55+
# - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/rockettile_icache_data_arrays_0_0/rockettile_icache_data_arrays_0_0_ext/mem_0_0"
56+
# type: hardmacro
57+
# x: 50
58+
# y: 2100
59+
# orientation: r90
60+
# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
61+
vlsi.inputs.power_spec_mode: "auto"
62+
vlsi.inputs.power_spec_type: "cpf"

‎vlsi/example-sky130.yml‎

Lines changed: 22 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1,53 +1,31 @@
1-
# Technology Setup
2-
# Technology used is Sky130
31
vlsi.core.technology: "hammer.technology.sky130"
42

5-
vlsi.core.max_threads: 12
3+
vlsi.core.max_threads: 32
64

75
# Technology paths
86
technology.sky130:
9-
#sky130A: "/home/ff/eecs251b/sky130/sky130A"
10-
#sram22_sky130_macros: "/home/ff/eecs251b/sky130/sram22_sky130_macros"
11-
drc_blackbox_srams: true
7+
sky130A: "/home/ff/ee198/ee198-20/sky130_col/open_pdks-2022.10/share/pdk/sky130A"
8+
# sram22_sky130_macros: "/tools/commercial/skywater/local/chipyard-tutorial/sram22_sky130_macros"
9+
sram22_sky130_macros: "/home/ff/ee198/ee198-20/sky130_col/sram22_sky130_macros/"
10+
# https://github.com/rahulk29/sram22_sky130_macros/tree/dev
11+
12+
# this key is OPTIONAL, no NDA files will be used if it does not point to a valid path
13+
# sky130_nda: "/tools/commercial/skywater/swtech130/skywater-src-nda"
14+
15+
# for caravel collateral pulled in by this design
16+
caravel: /home/ff/ee198/ee198-20/sky130_col/caravel/v6.0
17+
1218
lvs_blackbox_srams: true
13-
#sky130_cds: "/home/ff/eecs151/fa23/pdk_final/sky130_cds/sky130_prelim_release_091123"
19+
sky130_scl: "/home/ff/ee198/ee198-20/sky130_col/sky130_scl_9T_0.0.6"
20+
sky130_cds: "/home/ff/ee198/ee198-20/sky130_col/sky130_release_0.0.4/"
21+
stdcell_library: "sky130_scl"
22+
#stdcell_library: "sky130_fd_sc_hd"
23+
24+
technology.core.stackup: "sky130_scl"
25+
vlsi.technology.placement_site: "CoreSite"
1426

15-
# SRAM compiler options
27+
# SRAM Compiler compiler options
1628
vlsi.core.sram_generator_tool: "hammer.technology.sky130.sram_compiler"
17-
vlsi.inputs.supplies.power: [ {name: "VDD", pins: ["VDD" ]},
18-
{name: "VPWR", pins: ["VPWR"], tie: "VDD"},
19-
{name: "VPB", pins: ["VPB" ], tie: "VDD"},
20-
{name: "HI", pins: ["HI" ], tie: "VDD"},
21-
{name: "vdd", pins: ["vdd" ], tie: "VDD"}]
22-
vlsi.inputs.supplies.ground: [ {name: "VSS", pins: ["VSS" ]},
23-
{name: "VGND", pins: ["VGND"], tie: "VSS"},
24-
{name: "LO", pins: ["LO"], tie: "VSS"},
25-
{name: "VNB", pins: ["VNB" ], tie: "VSS"},
26-
{name: "vss", pina: ["vss" ], tie: "VSS"}]
2729

28-
# TODO: fix the spice netlists for these SRAMS they currently reference rahul's bwrc nfs
29-
# vlsi.technology.extra_libraries:
30-
# - library:
31-
# nldm_liberty_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro_tt_025C_1v80.rc.lib"
32-
# verilog_sim: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.v"
33-
# lef_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.lef"
34-
# gds_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.gds"
35-
# corner: {nmos: typical, pmos: typical, temperature: "025 C"}
36-
# supplies: {VDD: "1.80 V", GND: "0 V"}
37-
# provides: [ {lib_type: stdcell, vt: RVT} ]
38-
# - library:
39-
# nldm_liberty_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro_tt_025C_1v80.rc.lib"
40-
# verilog_sim: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.v"
41-
# lef_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.lef"
42-
# gds_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.gds"
43-
# corner: {nmos: slow, pmos: slow, temperature: "100 C"}
44-
# supplies: {VDD: "1.60 V", GND: "0 V"}
45-
# provides: [ {lib_type: stdcell, vt: RVT} ]
46-
# - library:
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# nldm_liberty_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro_tt_025C_1v80.rc.lib"
48-
# verilog_sim: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.v"
49-
# lef_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.lef"
50-
# gds_file: "/scratch/eecs251b-aae/chipyard/vlsi/macros/sram22_64x32m4w32_macro/sram22_64x32m4w32_macro.gds"
51-
# corner: {nmos: fast, pmos: fast, temperature: "-40 C"}
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# supplies: {VDD: "1.95 V", GND: "0 V"}
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# provides: [ {lib_type: stdcell, vt: RVT} ]
30+
# this is because the io cells use virtual connect pin names for rails
31+
lvs.calibre.virtual_connect_colon: true

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