Commit c79fb4c
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Bump toolchains/riscv-tools/riscv-isa-sim from
Bumps [toolchains/riscv-tools/riscv-isa-sim](https://github.com/riscv-software-src/riscv-isa-sim) from `7812eab` to `3084a8e`.
- [Release notes](https://github.com/riscv-software-src/riscv-isa-sim/releases)
- [Commits](riscv-software-src/riscv-isa-sim@7812eab...3084a8e)
---
updated-dependencies:
- dependency-name: toolchains/riscv-tools/riscv-isa-sim
dependency-version: 3084a8e5499334c3aac1252aa76197432aacd6c5
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>7812eab to 3084a8e
1 parent cc16558 commit c79fb4c
1 file changed
+1
-1
lines changedSubmodule riscv-isa-sim updated 99 files
- .github/workflows/continuous-integration.yml+1-1
- .gitignore+1
- README.md+2-2
- ci-tests/custom-csr.cc+5-4
- ci-tests/test-customext.cc+5-4
- ci-tests/testlib.cc+2-1
- config.h.in+9-7
- configure+676-693
- configure.ac+10-16
- customext/cflush.cc+3-3
- customext/dummy_rocc.cc+4-4
- disasm/disasm.cc+194-206
- disasm/isa_parser.cc+2
- fesvr/htif.cc+51-34
- fesvr/htif.h+10-1
- fesvr/syscall.cc+2-2
- m4/ax_append_flag.m4
- m4/ax_append_link_flags.m4
- m4/ax_boost_asio.m4
- m4/ax_boost_base.m4+11-9
- m4/ax_boost_regex.m4
- m4/ax_check_compile_flag.m4+13-3
- m4/ax_check_link_flag.m4
- m4/ax_require_defined.m4
- riscv/abstract_device.h+1
- riscv/arith.h+3-3
- riscv/cfg.h+2
- riscv/csrs.cc+18-17
- riscv/csrs.h+1-1
- riscv/debug_module.cc+5
- riscv/debug_module.h+3-2
- riscv/devices.cc+93-32
- riscv/devices.h+31-5
- riscv/disasm.h+2-2
- riscv/encoding.h+30-2
- riscv/execute.cc+2-4
- riscv/extension.cc+4-10
- riscv/extension.h+10-13
- riscv/insns/bclri.h+1
- riscv/insns/bexti.h+1
- riscv/insns/binvi.h+1
- riscv/insns/bseti.h+1
- riscv/insns/mnret.h+6
- riscv/insns/ssrdp.h+1-1
- riscv/insns/vcompress_vm.h+5-5
- riscv/insns/vfrsqrt7_v.h+1-1
- riscv/insns/vnsra_wi.h+1-1
- riscv/insns/vqdot_common.h+15
- riscv/insns/vqdot_vv.h+11
- riscv/insns/vqdot_vx.h+11
- riscv/insns/vqdotsu_vv.h+11
- riscv/insns/vqdotsu_vx.h+11
- riscv/insns/vqdotu_vv.h+11
- riscv/insns/vqdotu_vx.h+11
- riscv/insns/vqdotus_vx.h+11
- riscv/insns/vsll_vi.h+2-2
- riscv/insns/vsll_vv.h+1-1
- riscv/insns/vsll_vx.h+1-1
- riscv/insns/vsrl_vi.h+1-1
- riscv/insns/vssra_vi.h+1-1
- riscv/insns/vssrl_vi.h+1-1
- riscv/isa_parser.h+1
- riscv/jtag_dtm.h+3-1
- riscv/mmu.cc+23-17
- riscv/mmu.h+9-6
- riscv/processor.cc+17-9
- riscv/processor.h+3-2
- riscv/riscv.ac+1-1
- riscv/riscv.mk.in+10
- riscv/rocc.cc+5-5
- riscv/rocc.h+6-6
- riscv/sim.cc+19-5
- riscv/sim.h+10-3
- riscv/zicfiss.h+1-1
- scripts/config.guess+716-607
- scripts/config.sub+206-100
- scripts/install-sh+541
- scripts/install.sh-238
- softfloat/bf16_classify.c+36
- softfloat/bf16_cmp.c+65
- softfloat/bf16_to_i32.c+48
- softfloat/bf16_to_i8.c+57
- softfloat/bf16_to_ui32.c+48
- softfloat/bf16_to_ui8.c+54
- softfloat/f128_classify.c
- softfloat/f16_classify.c
- softfloat/f32_classify.c
- softfloat/f64_classify.c
- softfloat/fall_maxmin.c+16
- softfloat/fall_reciprocal.c+80
- softfloat/fall_sign.c+63
- softfloat/i32_to_bf16.c+52
- softfloat/internals.h+10-5
- softfloat/softfloat.h+18
- softfloat/softfloat.mk.in+9
- softfloat/specialize.h+7
- softfloat/ui32_to_bf16.c+51
- spike_dasm/spike-dasm.cc+3-1
- spike_main/spike.cc+8-2
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