diff --git a/build.sbt b/build.sbt index 51542d71..5c83ecae 100644 --- a/build.sbt +++ b/build.sbt @@ -408,6 +408,7 @@ lazy val firechip = (project in file("generators/firechip/chip")) Test / testOptions += Tests.Argument("-oF") ) .settings(scalaTestSettings) + lazy val ofo = (project in file("generators/ofo")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/generators/chipyard/src/main/scala/config/OFOConfigs.scala b/generators/chipyard/src/main/scala/config/OFOConfigs.scala index ce59838d..03cb53af 100644 --- a/generators/chipyard/src/main/scala/config/OFOConfigs.scala +++ b/generators/chipyard/src/main/scala/config/OFOConfigs.scala @@ -5,52 +5,43 @@ import freechips.rocketchip.subsystem.{InCluster} import testchipip.boot.{BootAddrRegKey, BootAddrRegParams} import freechips.rocketchip.subsystem.{MBUS, SBUS} - import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} import freechips.rocketchip.devices.tilelink.{CLINTParams, CLINTKey} - - import freechips.rocketchip.subsystem.{ExtBus, ExtMem, MemoryPortParams, MasterPortParams, SlavePortParams, MemoryBusKey} // -------------- // OFO (EECS 151 ASIC) Core Configs // -------------- -class OFORocketConfig - extends Config( - new ofo.WithOFOCores(Seq(ofo.OneFiftyOneCoreParams(projectName="kevin-kore"))) ++ - - new freechips.rocketchip.rocket.WithNSmallCores(1) ++ // Add a small "control" core - new freechips.rocketchip.rocket.WithL1ICacheSets(64) ++ // 64 sets, 1 way, 4K cache - new freechips.rocketchip.rocket.WithL1ICacheWays(1) ++ - new freechips.rocketchip.rocket.WithL1DCacheSets(64) ++ // 64 sets, 1 way, 4K cache - new freechips.rocketchip.rocket.WithL1DCacheWays(1) ++ +class OFORawConfig extends Config( + new ofo.WithOFOCores(Seq(ofo.OneFiftyOneCoreParams(projectName="kevin-kore"))) ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ // make mem big enough for multiple binaries + new chipyard.config.AbstractConfig +) +class TemplateOFORocketConfig extends Config( + new freechips.rocketchip.rocket.WithNSmallCores(1) ++ // Add a small "control" core + new freechips.rocketchip.rocket.WithL1ICacheSets(64) ++ // 64 sets, 1 way, 4K cache + new freechips.rocketchip.rocket.WithL1ICacheWays(1) ++ + new freechips.rocketchip.rocket.WithL1DCacheSets(64) ++ // 64 sets, 1 way, 4K cache + new freechips.rocketchip.rocket.WithL1DCacheWays(1) ++ new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ // make mem big enough for multiple binaries - // TODO: make tinycore work, currently at least printing doesn't work persumably bc of the cache being a spad that TSI can't access (and thus can't print from) + new chipyard.config.AbstractConfig +) - new chipyard.config.AbstractConfig - ) -class OFORawConfig - extends Config( - new ofo.WithOFOCores(Seq(ofo.OneFiftyOneCoreParams(projectName="kevin-kore"))) ++ - - new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++ // make mem big enough for multiple binaries - new chipyard.config.AbstractConfig - ) - -class OFOTConfig extends Config( // toplevel -//TODO Remove Simulation collateral +class TemplateOFOTConfig extends Config( // toplevel + //TODO Remove Simulation collateral new chipyard.sky130.WithVerilogDummySky130EFCaravelPOR ++ -// heavily referencing STACConfig and ChipLikeConfig -// don't have enough area for these + // heavily referencing STACConfig and ChipLikeConfig + // don't have enough area for these new chipyard.config.WithBroadcastManager ++ // Replace L2 with a broadcast hub for coherence new testchipip.soc.WithNoScratchpads ++ // No scratchpads - //================================== + + //================================== // Set up I/O //================================== new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams( // 1 serial tilelink port @@ -77,13 +68,42 @@ class OFOTConfig extends Config( // toplevel new testchipip.soc.WithOffchipBusClient(MBUS) ++ // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory new testchipip.soc.WithOffchipBus ++ // attach a offchip bus, since the serial-tl will master some external tilelink memory - // set up io ring - new chipyard.sky130.WithSky130EFIOCells(sim = false) ++ - new chipyard.sky130.WithSky130EFIOTotalCells(46) ++ - new chipyard.sky130.WithSky130ChipTop ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - - // actually include the ofo core and tiny rocket - new OFORocketConfig - ) + new chipyard.sky130.WithSky130EFIOCells(sim = false) ++ + new chipyard.sky130.WithSky130EFIOTotalCells(46) ++ + new chipyard.sky130.WithSky130ChipTop ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology +) + +class ProvenOFOTConfig extends Config( + // SoC harness + new TemplateOFOTConfig ++ + // actually include the ofo core + new ofo.WithOFOCores(Seq(ofo.OneFiftyOneCoreParams(projectName="kevin-kore"))) ++ + // actually include the tiny rocket + new TemplateOFORocketConfig +) + +// -------------- +// More experimental OFO Configs +// -------------- + +class DualOFOTConfig extends Config( + // SoC harness + new TemplateOFOTConfig ++ + // actually include the ofo core + new ofo.WithOFOCores(Seq(ofo.OneFiftyOneCoreParams(projectName="kevin-kore"), + ofo.OneFiftyOneCoreParams(projectName="kevin-kore"))) ++ + // actually include the tiny rocket + new TemplateOFORocketConfig +) + +class MultiOFOTConfig extends Config( + // SoC harness + new TemplateOFOTConfig ++ + // actually include the ofo core + new ofo.WithOFOCores(Seq(ofo.OneFiftyOneCoreParams(projectName="kevin-kore"), + ofo.OneFiftyOneCoreParams(projectName="fa23-mechanical-engineering-main"))) ++ + // actually include the tiny rocket + new TemplateOFORocketConfig +) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 8517fc1d..cff6e2ba 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -100,3 +100,12 @@ clean-sim: clean-sim-debug: rm -rf $(model_dir_debug) $(build_dir)/vc_hdrs.h $(sim_debug) $(sim_debug).daidir ucli.key + +######################################################################################### +# OFOT running VCS flag +######################################################################################### + +# Define a flag to indicate the simulation Makefile is being run +RUN_TYPE_FLAG =sim +# Export the flag so it can be accessed outside the Makefile +export RUN_TYPE_FLAG \ No newline at end of file diff --git a/vlsi/Makefile b/vlsi/Makefile index 29c86d07..67d354be 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -218,3 +218,12 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) .PHONY: clean clean: rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(CLASSPATH_CACHE) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) + +######################################################################################### +# OFOT running VLSI flag +######################################################################################### + +# Define a flag to indicate the VLSI (non-sim) Makefile is being run +RUN_TYPE_FLAG =pd +# Export the flag so it can be accessed outside the Makefile +export RUN_TYPE_FLAG \ No newline at end of file diff --git a/vlsi/hammer-driver b/vlsi/hammer-driver index d9d84949..0297232c 100755 --- a/vlsi/hammer-driver +++ b/vlsi/hammer-driver @@ -303,9 +303,6 @@ class Driver(CLIDriver): HammerTool.make_pre_insertion_hook("syn_generic", derate_srams), HammerTool.make_pre_insertion_hook("syn_generic", flatten_analog_driver), HammerTool.make_pre_insertion_hook("syn_generic", chiptop_dont_touch), - - HammerTool.make_persistent_hook(patch_hvl_ls_lef), # abuse persistent steps to chuck stuff in cache - # manually include the LEFs for the srams used by the 151 core since sram_compiler doesn't know about them HammerTool.make_persistent_hook(add_ofo_srams), ] @@ -350,8 +347,6 @@ class Driver(CLIDriver): # Not needed with manual CPF flow HammerTool.make_removal_hook("sky130_connect_nets"), HammerTool.make_removal_hook("sky130_connect_nets2"), - - HammerTool.make_persistent_hook(patch_hvl_ls_lef), # abuse persistent steps to chuck stuff in cache ] def get_extra_drc_hooks(self) -> List[HammerToolHookAction]: