diff --git a/vlsi/hammer b/vlsi/hammer
index b2493dff..0f5388ed 160000
--- a/vlsi/hammer
+++ b/vlsi/hammer
@@ -1 +1 @@
-Subproject commit b2493dfff6f3aa659b135a5c7c995afe7cea4c5f
+Subproject commit 0f5388ed185e52254bfabe7c127b73aedfd26d90
diff --git a/vlsi/tech-sky130-inst.yml b/vlsi/tech-sky130-inst.yml
index 2ec34da5..20d163a2 100644
--- a/vlsi/tech-sky130-inst.yml
+++ b/vlsi/tech-sky130-inst.yml
@@ -4,9 +4,10 @@ vlsi.core.max_threads: 32
 
 # Technology paths
 technology.sky130:
-  sky130A: "/home/ff/ee198/ee198-20/sky130_col/open_pdks-2022.10/share/pdk/sky130A"
+  # sky130A: "/home/ff/ee198/ee198-20/sky130_col/open_pdks-2022.10/share/pdk/sky130A"
+  sky130A: "/home/ff/ee198/ee198-20/sky130_col/open_pdks-2022.10/share/pdk/sky130A" # patched version for voltus run, otherwise no difference
   # sram22_sky130_macros: "/tools/commercial/skywater/local/chipyard-tutorial/sram22_sky130_macros"
-  sram22_sky130_macros: "/home/ff/ee198/ee198-20/sky130_col/sram22_sky130_macros/"
+  sram22_sky130_macros: "/home/ff/ee198/ee198-20/sky130_col/sram22_sky130_macros"
   # https://github.com/rahulk29/sram22_sky130_macros/tree/dev
 
   # this key is OPTIONAL, no NDA files will be used if it does not point to a valid path
@@ -16,8 +17,13 @@ technology.sky130:
   caravel: /home/ff/ee198/ee198-20/sky130_col/caravel/v6.0
 
   lvs_blackbox_srams: true
-  sky130_scl: "/home/ff/ee198/ee198-20/sky130_col/sky130_scl_9T_0.0.6"
-  sky130_cds: "/home/ff/ee198/ee198-20/sky130_col/sky130_release_0.0.4/"
+  sky130_scl: "/home/ff/ee198/ee198-20/sky130_col/sky130_scl_9T_0.1.2"
+  sky130_cds: "/home/ff/ee198/ee198-20/sky130_col/sky130_release_0.0.9"
+  # seal ring layout and layouts for creating a die ID
+  sky130_cds_die_collateral: "/home/ff/ee198/ee198-20/sky130_col/sky130_die_collateral_1.0"
+  drc_deck_sources: [
+    "$SKY130_CDS/Sky130_DRC/sky130_rev_0.0_2.10.drc.pvl",
+  ]
   stdcell_library: "sky130_scl"
   #stdcell_library: "sky130_fd_sc_hd"
   
@@ -79,24 +85,22 @@ vlsi.technology.override_libraries:
   - library:
       gds_file: ["/home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_ef_io_with_overlay.gds", "sky130_ef_io.gds"]
       # this is hacked in sky130/__init__.py
-      #lef_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef
+      # lef_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef
       spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_ef_io.spice
   - library:
       spice_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/sky130_fd_sc_hd.cdl
 vlsi.technology.extra_libraries_meta: ["append", "lazydeepsubst"]
 vlsi.technology.extra_libraries:
-  - library:
-      gds_file: /home/ff/ee198/ee198-20/sky130_col/FILL16.gds
-  - library:
-      gds_file: /home/ff/ee198/ee198-20/sky130_col/FILL4.gds
-  - library:
-      gds_file: /home/ff/ee198/ee198-20/sky130_col/FILL1.gds
   - library:
       spice_file: /home/ff/ee198/ee198-20/sky130_col/stac_misc_collat/devices.sp
   - library: # TODO: why is this required? seems like it isn't used in stacv2 repo
       spice_file: ${technology.sky130.sram22_sky130_macros}/sram22.spice
   - library:
       spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_fd_io.spice
+  - library: 
+      spice_file: /home/ff/ee198/ee198-20/sky130_col/open_pdks-2022.10/share/pdk/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
+  - library:
+      spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_ef_io__gpiov2_pad_wrapped.sp
   - library:
       <<: *lib__sky130_fd_sc_hvl__lsbufhv2lv
       nldm_liberty_file: ${technology.sky130.sky130A}/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_100C_1v65_lv1v60.lib
@@ -140,8 +144,9 @@ vlsi.technology.extra_libraries:
   - library:
       gds_file: ${technology.sky130.caravel}/gds/simple_por.gds
       lef_file: ${technology.sky130.caravel}/lef/simple_por.lef
+      # spice_file: /scratch/ee198-20-aaf/sky130_col/io_lvs/simple_por.spice
       spice_file: /home/ff/ee198/ee198-20/sky130_col/io_lvs/sky130_ef_io.spice
-      verilog_sim: ${technology.sky130.caravel}/verilog/rtl/simple_por.v
+      # verilog_sim: ${technology.sky130.caravel}/verilog/rtl/simple_por.v
       provides:
         - lib_type: por
-          vt: RVT
+          vt: RVT
\ No newline at end of file