Skip to content

Commit 86f2248

Browse files
Merge pull request #254 from uclid-org/fix-253
Fix data type hashing; fix 253
2 parents 289628e + a063957 commit 86f2248

File tree

3 files changed

+24
-4
lines changed

3 files changed

+24
-4
lines changed

src/main/scala/uclid/smt/SMTLanguage.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -201,8 +201,8 @@ case object UndefinedType extends Type {
201201

202202
case class DataType(id : String, cstors : List[ConstructorType]) extends Type {
203203
override val hashId = 111
204-
override val hashCode = finalize(hashId, 0)
205-
override val md5hashCode = computeMD5Hash
204+
override val hashCode = computeHash(id, cstors)
205+
override val md5hashCode = computeMD5Hash(id, cstors)
206206
override def toString = "data " + cstors // TODO
207207
override val typeNamePrefix = "data"
208208
override def isUndefined = true

src/test/scala/SMTLIB2Spec.scala

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -445,14 +445,15 @@ class SMTLIB2Spec extends AnyFlatSpec {
445445
"issue-187b.ucl" should "verify all assertions." in {
446446
SMTLIB2Spec.expectedFails("./test/issue-187b.ucl", 0)
447447
}
448+
"issue-253.ucl" should "fail all 2 assertions." in {
449+
SMTLIB2Spec.expectedFails("./test/issue-253.ucl", 2)
450+
}
448451
"issue-255.ucl" should "faill single assertion." in {
449452
SMTLIB2Spec.expectedFails("./test/issue-255.ucl", 1)
450453
}
451454
"test-redundant-assign.ucl" should "verify all assertions." in {
452455
SMTLIB2Spec.expectedFails("./test/test-redundant-assign.ucl", 0)
453456
}
454-
455-
456457
"test-history-1.ucl" should "verify all assertions." in {
457458
SMTLIB2Spec.expectedFails("./test/test-history-1.ucl", 0)
458459
}

test/issue-253.ucl

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
module main {
2+
datatype adt1 = A() | B();
3+
datatype adt2 = C() | D();
4+
5+
var y: adt1;
6+
var x: adt2;
7+
8+
init {
9+
assert y == B();
10+
assert x == C();
11+
}
12+
13+
14+
control {
15+
bmc(0);
16+
check;
17+
print_results;
18+
}
19+
}

0 commit comments

Comments
 (0)