Integrating RISC-V Debug (DM/DTM)

[UHRmm]

Hi, thanks a lot for releasing the RV32IM core — it’s been very helpful.
I’d like to add RISC-V external debug (spec 0.13.x) to the core.

1. Are there existing debug hooks (halt/resume, dcsr/dpc, single-step)?
2. Any recommended DM/DTM IP or reference integrations?
3. Any known limitations or preferred hookup guidance?

Many thanks!