Register Maximal width is wrongly supported

[richnou]

The Register Width can be defined in RFG to support and data width interface.
However, if a register exceeds this size, the API does not produce an error, and the produced Verilog generates too wide data buses.

When synthesizing the design, the bits in registers over the maximal size may be trimmed away, and this can only be seen in a warning, making design debugging difficult.

Solution: Registers wider than maximal register size should just produce an error during definition parsing.