test: verilog file with gate level models

still broken though - see google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0#26

Author: urish

test/Makefile

@@ -18,7 +18,7 @@ COMPILE_ARGS    += -DFUNCTIONAL
 COMPILE_ARGS    += -DUSE_POWER_PINS
 COMPILE_ARGS    += -DSIM
 COMPILE_ARGS    += -DUNIT_DELAY=#1
-VERILOG_SOURCES += $(PDK_ROOT)/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/gf180mcu_fd_sc_mcu7t5v0.v
+VERILOG_SOURCES += $(PWD)/gf180mcu_fd_sc_mcu7t5v0.v
 
 # the github action copies the gatelevel verilog from /runs/wokwi/results/final/verilog/gl/ 
 VERILOG_SOURCES += $(PWD)/cell_tb_gl.v $(PWD)/../verilog/gl/tiny_user_project.v

test/cell_tb.gtwk

@@ -0,0 +1,28 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Mon Nov 28 18:18:35 2022
+[*]
+[dumpfile] "/home/uri/p/gf180-game-of-life-cell/test/cell_tb.vcd"
+[dumpfile_mtime] "Mon Nov 28 18:17:20 2022"
+[dumpfile_size] 425020
+[savefile] "/home/uri/p/gf180-game-of-life-cell/test/cell_tb.gtwk"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-12.307270 4250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] test_cell.
+[sst_width] 214
+[signals_width] 142
+[sst_expanded] 1
+[sst_vpaned_height] 152
+@28
+test_cell.clk
+test_cell.reset
+test_cell.set
+@22
+test_cell.neighbors[7:0]
+@28
+test_cell.alive
+test_cell.notalive
+[pattern_trace] 1
+[pattern_trace] 0