Skip to content

Commit a18f2c9

Browse files
vChavezBvChavezB
authored
Merge pull request #2 from vChavezB/alpha
Updated main branch to alpha v1.0.0
2 parents c86b0ea + 26d99dc commit a18f2c9

31 files changed

+2394
-2
lines changed

‎.github/workflows/demo_build.yml‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# Copyright (c) 2024, Victor Chavez
2+
# SPDX-License-Identifier: GPL-3.0-or-later
3+
4+
name: Build Demo
5+
6+
on:
7+
push:
8+
pull_request:
9+
10+
jobs:
11+
12+
build:
13+
runs-on: ubuntu-22.04
14+
container: ghcr.io/zephyrproject-rtos/ci:v0.26.2
15+
env:
16+
CMAKE_PREFIX_PATH: /opt/toolchains
17+
ZEPHYR_VERSION: v3.6-branch
18+
# Board to use with renode
19+
BOARD: nrf52833dk_nrf52833
20+
steps:
21+
- name: Checkout
22+
uses: actions/checkout@v4
23+
with:
24+
submodules: true
25+
- name: Initialize
26+
run: |
27+
cd /tmp/
28+
west init
29+
west update -o=--depth=1 -n
30+
31+
- name: Build PoC
32+
working-directory: /tmp/
33+
run: |
34+
west build $GITHUB_WORKSPACE/samples/demo -b $BOARD --build-dir $GITHUB_WORKSPACE/build

‎.github/workflows/samples_build.yml‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# Copyright (c) 2024, Victor Chavez
2+
# SPDX-License-Identifier: GPL-3.0-or-later
3+
4+
name: Build Samples
5+
6+
on:
7+
push:
8+
pull_request:
9+
10+
jobs:
11+
12+
read_pd:
13+
runs-on: ubuntu-22.04
14+
container: ghcr.io/zephyrproject-rtos/ci:v0.26.2
15+
env:
16+
CMAKE_PREFIX_PATH: /opt/toolchains
17+
ZEPHYR_VERSION: v3.6-branch
18+
# Board to use with renode
19+
BOARD: nrf52833dk_nrf52833
20+
steps:
21+
- name: Checkout
22+
uses: actions/checkout@v4
23+
with:
24+
submodules: true
25+
- name: Initialize
26+
run: |
27+
cd /tmp/
28+
west init
29+
west update -o=--depth=1 -n
30+
31+
- name: Build PoC
32+
working-directory: /tmp/
33+
run: |
34+
west build $GITHUB_WORKSPACE/samples/read_pd -b $BOARD --build-dir $GITHUB_WORKSPACE/build

‎.gitignore‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
samples/*/build*
2+
*.vscode
3+
# Prerequisites
4+
*.d
5+
6+
# Compiled Object files
7+
*.slo
8+
*.lo
9+
*.o
10+
*.obj
11+
12+
# Precompiled Headers
13+
*.gch
14+
*.pch
15+
16+
# Compiled Dynamic libraries
17+
*.so
18+
*.dylib
19+
*.dll
20+
21+
# Fortran module files
22+
*.mod
23+
*.smod
24+
25+
# Compiled Static libraries
26+
*.lai
27+
*.la
28+
*.a
29+
*.lib
30+
31+
# Executables
32+
*.exe
33+
*.out
34+
*.app
35+
36+
*/build/*

‎.gitmodules‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
[submodule "i-link"]
2+
path = i-link
3+
url = https://github.com/vChavezB/i-link/

‎CMakeLists.txt‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
# Copyright (c) 2024 Victor Chavez
2+
# SPDX-License-Identifier: GPL-3.0-or-later
3+
4+
if(CONFIG_IOLINK)
5+
set(lib_name iolink_master)
6+
set(OSAL_DIR ${CMAKE_CURRENT_SOURCE_DIR}/osal)
7+
set(IOL_OSAL_DIR ${CMAKE_CURRENT_SOURCE_DIR}/iol_osal)
8+
set(STACK_DIR ${CMAKE_CURRENT_SOURCE_DIR}/i-link)
9+
set(STACK_SRC ${STACK_DIR}/src)
10+
zephyr_library_named(${lib_name})
11+
# todo separate private and public
12+
zephyr_include_directories( ${STACK_DIR}/include
13+
${STACK_DIR}/include/src
14+
${STACK_DIR}/src
15+
${STACK_DIR}/iol_osal/include
16+
${CMAKE_CURRENT_SOURCE_DIR}/src/osal
17+
${CMAKE_CURRENT_SOURCE_DIR}/src
18+
include
19+
)
20+
21+
zephyr_library_sources(${STACK_SRC}/iolink_al.c
22+
${STACK_SRC}/iolink_cm.c
23+
${STACK_SRC}/iolink_dl.c
24+
${STACK_SRC}/iolink_ds.c
25+
${STACK_SRC}/iolink_main.c
26+
${STACK_SRC}/iolink_max14819_pl.c
27+
${STACK_SRC}/iolink_ode.c
28+
${STACK_SRC}/iolink_pde.c
29+
${STACK_SRC}/iolink_pl.c
30+
${STACK_SRC}/iolink_sm.c
31+
src/osal/osal.c
32+
src/osal/osal_log.c
33+
src/iolm.c
34+
src/utils.c
35+
src/transciever.c)
36+
37+
#zephyr_library_sources_ifdef(CONFIG_XX xx)
38+
#target_compile_definitions(${lib_name} PUBLIC MY_DEF="123")
39+
target_include_directories(${lib_name} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/dts/bindings/iolm)
40+
target_compile_options(${lib_name} PRIVATE -Wfatal-errors)
41+
endif()
42+

‎README.md‎

Lines changed: 38 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,44 @@ This repository integrates a [forked](https://github.com/vChavezB/i-link/tree/ze
44

55
## Supported PHYS
66

7-
The RT-Labs stack only supports the MAX14189 PHY. This requires only from the Zephyr board side an SPI interface and an IRQ pin.
7+
The RT-Labs stack only supports the MAX14189 PHY. This requires a Zephyr board that has an SPI interface and GPIOs for the Chip select and IRQ.
8+
9+
## License
10+
11+
The IO-Link stack (i.e., backend) is provided by RT-Labs as GPLv3.0. Hence This Zephyr port
12+
is also licensed as GPLv3.0.
13+
14+
## Tested boards
15+
16+
- ESP32 Devkit C
17+
- NRF52833 DK
18+
19+
Zephyr version v3.6.99 commit `34c84eccec0508b16f5001b20fa369f387d856df`
20+
21+
## Testing
22+
23+
A sample to test the current API for this project is located in `samples/read_pd`.
824

925
## Current Status
1026

11-
This repository is under development and will not provide a stable API until the first release version.
27+
This project is in alpha version and will not provide a stable API/Documentation until the first release.
28+
29+
Currently building API to use easily the IOLM Stack.
30+
31+
## Issues
32+
33+
- Legacy devices (V.1.0) do not go to operate. Some tests have been done and it seems
34+
that the RT-Labs stack cannot process events for legacy devices. The device goes to operate
35+
but the System Managemen (SM) and SMI Configuration Management (CM) do not report back this change.
36+
This happens as it seems that the OD Handler for the event state machine gets stuck.
37+
38+
39+
### TODOS
40+
41+
- Test Port Cfg with Validation (VID,DID, V10,V11)
42+
- Wrapper for direct access to SMI Requests
43+
- Test SMI Device Read/Write
44+
45+
46+
47+

‎dts/bindings/iolm/iol,maxim14819.yaml‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
# Copyright (c) 2024 Victor Chavez
2+
# SPDX-License-Identifier: GPL-3.0-or-later
3+
4+
description: >
5+
Binding for the MAXIM14819 IOLM Transciever
6+
7+
compatible: "iolm,maxim14819"
8+
9+
include: [ spi-device.yaml ]
10+
11+
properties:
12+
irq-gpios:
13+
type: phandle-array
14+
required: true
15+
description: GPIO pin used for irq
16+
17+
18+
chip-address:
19+
description: SPI address of the transceiver
20+
type: int
21+
required: true
22+
23+
IntE:
24+
description: Initial value of the InterruptEn register
25+
type: int
26+
27+
CQCtrlA:
28+
description: Initial value of the CQCtrlA register
29+
type: int
30+
31+
CQCtrlB:
32+
description: Initial value of the CQCtrlB register
33+
type: int
34+
35+
LEDCtrl:
36+
description: Initial value of the LEDCtrl register
37+
type: int
38+
39+
CQCfgA:
40+
description: Initial value of the CQCfgA register
41+
type: int
42+
43+
CQCfgB:
44+
description: Initial value of the CQCfgB register
45+
type: int
46+
47+
LPCnfgA:
48+
description: Initial value of the LPCnfgA register
49+
type: int
50+
51+
LPCnfgB:
52+
description: Initial value of the LPCnfgB register
53+
type: int
54+
55+
IOStCfgA:
56+
description: Initial value of the IOStCfgA register
57+
type: int
58+
59+
IOStCfgB:
60+
description: Initial value of the IOStCfgB register
61+
type: int
62+
63+
DrvCurrLim:
64+
description: Initial value of the DrvCurrLim register
65+
type: int
66+
67+
Clock:
68+
description: Initial value of the Clock register
69+
type: int

‎dts/bindings/iolm/maxim14819.h‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
/* Copyright (c) 2024 Victor Chavez
2+
SPDX-License-Identifier: GPL-3.0-or-later
3+
*/
4+
#define CQCFG_CQFILTEREN BIT(0)
5+
#define CQCFG_DRVDIS BIT(1)
6+
#define CQCFG_PUSHPUL BIT(2)
7+
#define CQCFG_NPN BIT(3)
8+
#define CQCFG_SINKSEL(x) (((x) & 0x03) << 4)
9+
#define CQCFG_SINKSEL_MASK CQCFG_SINKSEL (0x3)
10+
#define CQCFG_SOURCESINK BIT(6)
11+
#define CQCFG_IEC3TH BIT(7)
12+
13+
#define CLOCK_XTALEN BIT (0)
14+
#define CLOCK_EXTCLKEN BIT (1)
15+
#define CLOCK_CLKDIV(x) (((x) & 0x03) << 2)
16+
#define CLOCK_CLKDIV_MASK CLOCK_CLKDIV (0x03)
17+
#define CLOCK_CLKOEN BIT (4)
18+
#define CLOCK_EXTCLKMIS BIT (5)
19+
#define CLOCK_TXTXENDIS BIT (6)
20+
#define CLOCK_VCCWARNEN BIT (7)
21+
22+
#define IOSTCFG_DICSINK BIT (0)
23+
#define IOSTCFG_DICSOURCE BIT (1)
24+
#define IOSTCFG_DIEC3TH BIT (2)
25+
#define IOSTCFG_DIFILTEREN BIT (3)
26+
#define IOSTCFG_TX BIT (4)
27+
#define IOSTCFG_TXEN BIT (5)
28+
#define IOSTCFG_CQLEVEL BIT (6)
29+
#define IOSTCFG_DILEVEL BIT (7)
30+
31+
#define LPCNFG_LPEN BIT (0)
32+
#define LPCNFG_LPCLIMDIS BIT (1)
33+
#define LPCNFG_LPCL2X BIT (2)
34+
#define LPCNFG_LPBL(x) (((x) & 0x03) << 3)
35+
#define LPCNFG_LPBL_MASK LPCNFG_BLA (0x03)
36+
#define LPCNFG_LPDYNBL BIT (5)
37+
#define LPCNFG_LPRT(x) (((x) & 0x03) << 6)
38+
#define LPCNFG_LPRT_MASK LPCNFG_BLA (0x03)
39+
40+
#define CURR_100MA 0x00
41+
#define CURR_200MA 0x01
42+
#define CURR_300MA 0x02
43+
#define CURR_500MA 0x03
44+
#define DRVRCURRLIM_CLDIS BIT(5)
45+
46+
#define CURR_OFF 0x06
47+
48+
#define CL_CONF(x) ((x) << CURR_OFF)

‎i-link‎

Submodule i-link added at 4fe9be0

‎include/iolm/iolm.h‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
/* Copyright (c) 2024 Victor Chavez
2+
SPDX-License-Identifier: GPL-3.0-or-later
3+
*/
4+
#pragma once
5+
6+
#include <stdint.h>
7+
#include <stddef.h>
8+
#include <iolink.h>
9+
#include <iolink_types.h>
10+
11+
struct iolm_port_cfg {
12+
uint16_t vid; // Required if validation = IOLINK_VALIDATION_CHECK_V11_RESTORE or IOLINK_VALIDATION_CHECK_V11_BAK_RESTORE
13+
uint32_t did; // Required if validation = IOLINK_VALIDATION_CHECK_V11_RESTORE or IOLINK_VALIDATION_CHECK_V11_BAK_RESTORE
14+
uint32_t cycle_time_us; // Desired cycle time in microseconds, initialize to 0 if you want to set As fast as Possible
15+
iolink_portmode_t portmode;
16+
iolink_validation_check_t validation;
17+
};
18+
19+
20+
enum iolm_port_evt{
21+
IOLM_PORT_PD= 0, // New PD cycle data available
22+
IOLM_PORT_STATUS, // Port status changed
23+
IOLM_PORT_DEV_EVT // Device event
24+
};
25+
26+
struct iolm_pd_data {
27+
const uint8_t * data;
28+
size_t len;
29+
};
30+
31+
/**
32+
* @brief IO-Link Device event entry
33+
*
34+
*/
35+
struct iolm_evt_entry {
36+
iolink_event_mode_t mode;
37+
iolink_event_type_t type;
38+
uint16_t event_code;
39+
};
40+
41+
/**
42+
* @brief IO-Link Master device event
43+
*
44+
*/
45+
struct iolm_dev_evt {
46+
struct iolm_evt_entry * entry;
47+
size_t len;
48+
};
49+
50+
/**
51+
* @brief IO-Link Master port event callback
52+
*
53+
*/
54+
typedef void (*iolm_port_evt_cb)(uint8_t port, enum iolm_port_evt evt, void *data, void *arg);
55+
56+
/**
57+
* @brief Initialize the IO-Link Master
58+
* @param init_cfg Initial configuration for the IO-Link ports. If NULL is passed
59+
* all the ports will be set to IOLINK_PORTMODE_IOL_AUTO and the cycle time as fast as possible
60+
* @return 0 on success
61+
* -ENODEV When a driver fails to initialize or Master struct failed to initialize
62+
* -EIO When port configuration failed
63+
*/
64+
int iolm_init(const struct iolm_port_cfg * init_cfg);
65+
66+
/**
67+
* @brief Set the IO-Link Master port event callback
68+
*
69+
* @param cb Callback function
70+
* @param arg Argument to be passed to the callback
71+
*/
72+
void iolm_set_port_evt_cb(iolm_port_evt_cb cb, void * arg);
73+

0 commit comments

Comments
 (0)