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Harden SIMD admission notes
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docs/SIMD_ACTIVATION_CHECKLIST.md

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@@ -50,6 +50,12 @@ caller-derived values to callee-saved vector registers, the admission package
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must also account for any compiler-generated spill/restore slots and prove that
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those slots are wiped or never contain caller-derived data.
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For Windows x64 specifically, XMM6 through XMM15 are callee-saved. AVX2 or
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AVX-512 admission on MSVC targets must prove that compiler-generated
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callee-saved XMM spill/restore slots do not retain caller-derived vector
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values, or use an ABI boundary that prevents those spills from carrying
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secret-bearing intermediates.
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For wasm `simd128`, source-level register cleanup is not sufficient evidence.
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The wasm runtime/JIT owns final register allocation and may rewrite the
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generated code. A wasm backend cannot be admitted until the selected runtime

src/scalar.rs

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@@ -265,7 +265,7 @@ fn first_padding_index_unchecked(input: [u8; 4]) -> usize {
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false,
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"first_padding_index_unchecked called with no padding"
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);
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4
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0
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}
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}
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src/simd/x86.rs

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@@ -188,16 +188,16 @@ where
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scalar_encode_block::<A, 12, 16>(input, output);
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return;
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}
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debug_assert!(is_standard_or_url_safe_family::<A>());
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let mut staged = [
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input[0], input[1], input[2], input[3], input[4], input[5], input[6], input[7], input[8],
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input[9], input[10], input[11], 0, 0, 0, 0,
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];
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// SAFETY: `staged` and `output` are valid 16-byte arrays. The function's
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// target-feature contract enables SSSE3/SSE4.1. The loads and stores are
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// unaligned variants, and the shuffle mask uses `0x80` lanes only for
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// zero-filled bytes. The SIMD path is non-dispatchable test evidence.
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// SAFETY: fixed arrays bound the unaligned load/store, the target-feature
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// contract enables SSSE3/SSE4.1, and the Standard-family guard above runs
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// before the SIMD-only arithmetic mapper.
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unsafe {
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let input_vec = _mm_loadu_si128(staged.as_ptr().cast::<__m128i>());
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let shuffle = _mm_setr_epi8(2, 1, 0, -128, 5, 4, 3, -128, 8, 7, 6, -128, 11, 10, 9, -128);

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