Fix DfgVertex is not of expected type, but instead has type 'SPLICEPACKED'

[fede541]

Hi!

Lately I’ve been having an issue when trying to verilate certain constructs that use SystemVerilog structures and packages. Below, I’m providing an example that reproduces the error.

Top block:

typedef struct t_struct_0;
typedef struct t_struct_1;
typedef struct t_struct_2;

import verilisst_test_pkg::*;

module verilisst_test #(parameter NB_I_DATA = 64) (
    input                  i_clock,
    input                  i_reset,
    input  [NB_I_DATA-1:0] i_data [NUM_INST+1],
    output t_struct_2      o_data_struct_2
);

    genvar bn;
    generate
       for (bn=1;bn<=NUM_INST;bn++) begin : g_test
            t_struct_0  data_struct_0    [STRUCT0_NUM];
            t_struct_1  data_struct_1    [STRUCT1_NUM];

            for(genvar ii=0; ii<STRUCT0_NUM; ii++)
                assign o_data_struct_2.part_2_0[bn][ii] = data_struct_0[ii];

            for(genvar ii=0; ii<STRUCT1_NUM; ii++)
                assign o_data_struct_2.part_2_1[bn][ii] = data_struct_1[ii];

            verilisst_test_subblock u_verilisst_test_subblock (
                .i_clock        (i_clock      ),
                .i_reset        (i_reset      ),
                .i_data         (i_data[bn]   ),
                .o_data_struct_0(data_struct_0),
                .o_data_struct_1(data_struct_1)
            );

       end
    endgenerate
endmodule

Sub-block:

typedef struct t_struct_0;
typedef struct t_struct_1;
typedef struct t_struct_2;

import verilisst_test_pkg::*;

module verilisst_test_subblock #(parameter NB_I_DATA = 64) (
    input                  i_clock                      ,
    input                  i_reset                      ,
    input  [NB_I_DATA-1:0] i_data                       ,
    output t_struct_0      o_data_struct_0 [STRUCT0_NUM],
    output t_struct_1      o_data_struct_1 [STRUCT1_NUM]
);
    logic [NB_I_DATA-1:0] data_delay;

    always_ff @(posedge i_clock)
        begin
            if(i_reset)
                data_delay <= '0;
            else
                data_delay <= i_data;
        end
    generate
        for (genvar part = 0; part < STRUCT0_NUM; part++) begin : g_data_struct_0
            assign o_data_struct_0[part].part_0_0 = i_data[0];
            assign o_data_struct_0[part].part_0_1 = i_data[10:1];
            assign o_data_struct_0[part].part_0_2 = i_data[20:11];
            assign o_data_struct_0[part].part_0_3 = i_data[21];
            assign o_data_struct_0[part].part_0_4 = i_data[31:22];
        end
        for (genvar part = 0; part < STRUCT1_NUM; part++) begin : g_data_struct_1
            assign o_data_struct_1[part].part_1_0 = i_data[32];
            assign o_data_struct_1[part].part_1_1 = i_data[42:33];
            assign o_data_struct_1[part].part_1_2 = i_data[52:43];
            assign o_data_struct_1[part].part_1_3 = i_data[53];
            assign o_data_struct_1[part].part_1_4 = i_data[63:54];
        end
    endgenerate
endmodule

package:

package verilisst_test_pkg;
parameter WIDTH_1 = 10;
parameter WIDTH_2 = 10;
parameter WIDTH_3 = 10;
parameter WIDTH_4 = 10;
parameter WIDTH_5 = 10;
parameter WIDTH_6 = 10;
parameter NUM_INST = 10;
parameter STRUCT0_NUM = 10;
parameter STRUCT1_NUM = 10;
typedef struct {
   logic                part_0_0;
   logic [WIDTH_1-1:0]  part_0_1;
   logic [WIDTH_2-1:0]  part_0_2;
   logic                part_0_3;
   logic [WIDTH_3-1:0]  part_0_4;
} t_struct_0;

typedef struct {
   logic                part_1_0;
   logic [WIDTH_4-1:0]  part_1_1;
   logic [WIDTH_5-1:0]  part_1_2;
   logic                part_1_3;
   logic [WIDTH_6-1:0]  part_1_4;
} t_struct_1;

typedef struct {
   t_struct_0  part_2_0[1:NUM_INST][STRUCT0_NUM-1:0];
   t_struct_1  part_2_1[1:NUM_INST][STRUCT1_NUM-1:0];
} t_struct_2;

endpackage

This is the verilator command line that I used:

verilator -cc --build -j 8 --threads 1 -MAKEFLAGS libVverilisst_test.a -CFLAGS -fdiagnostics-color=always -CFLAGS -O3 -Wno-lint -Wno-widthconcat -Wno-unoptflat -Wno-timescalemod -Wno-multidriven -Wno-BLKANDNBLK --unroll-count 999999 --unroll-stmts 999999 --structs-packed -CFLAGS -fPIC --no-timing -fno-reloop --prefix Vverilisst_test -f input.vc

The input.vc file only contains the paths to the 3 files above.

The error that comes up in this example is this:

%Error: Internal Error: verilisst_test.sv:12:28: ../V3Dfg.h:355: DfgVertex is not of expected type, but instead has type 'SPLICEPACKED'
   12 |     output t_struct_2      o_data_struct_2
      |                            ^~~~~~~~~~~~~~~
                        ... See the manual at https://verilator.org/verilator_doc.html?v=5.044 for more assistance.
make: *** [Makefile:27: run] Error 1

Here is the output error using --debug on command line

Starting Verilator 5.044 2026-01-01 rev vUNKNOWN-built20260309 (mod)
- V3Options.cpp:2044: Reading Options File input.vc
- Verilator.cpp:677:  Option --verilate: Start Verilation
- V3File.cpp:229:        --check-times failed: no input obj_dir/Vverilisst_test__verFiles.dat
- V3ParseImp.cpp:301: parseFile: verilated_std_waiver
- V3PreShell.cpp:90:  Preprocessing ./verilated_std_waiver.vlt
- V3PreShell.cpp:143:     Reading ./verilated_std_waiver.vlt
- V3ParseImp.cpp:417: Lexing ./verilated_std_waiver.vlt
- V3ParseImp.cpp:301: parseFile: verilated_std
- V3PreShell.cpp:90:  Preprocessing ./verilated_std.sv
- V3PreShell.cpp:143:     Reading ./verilated_std.sv
- V3ParseImp.cpp:417: Lexing ./verilated_std.sv
- V3ParseImp.cpp:301: parseFile: verilisst_test_subblock
- V3PreShell.cpp:90:  Preprocessing ./verilisst_test_subblock.sv
- V3PreShell.cpp:143:     Reading ./verilisst_test_subblock.sv
- V3ParseImp.cpp:373: Writing all preprocessed output to obj_dir/Vverilisst_test__inputs.vpp
- V3ParseImp.cpp:417: Lexing ./verilisst_test_subblock.sv
- V3ParseImp.cpp:301: parseFile: verilisst_test
- V3PreShell.cpp:90:  Preprocessing ./verilisst_test.sv
- V3PreShell.cpp:143:     Reading ./verilisst_test.sv
- V3ParseImp.cpp:417: Lexing ./verilisst_test.sv
- V3ParseImp.cpp:301: parseFile: verilisst_test_pkg
- V3PreShell.cpp:90:  Preprocessing ./verilisst_test_pkg.sv
- V3PreShell.cpp:143:     Reading ./verilisst_test_pkg.sv
- V3ParseImp.cpp:417: Lexing ./verilisst_test_pkg.sv
- V3LinkCells.cpp:473:Link --top-module: MODULE 0x1492110 <e1362#> {g8ai} u1=0x14a8870  verilisst_test  L0 D0 [NONE]
- V3Global.cpp:157:   Removing unused std:: package
- V3LinkLevel.cpp:42: modSortByLevel()
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_002_cellsort.tree
- V3LinkDot.cpp:5640: linkDotPrimary:
- V3LinkJump.cpp:483: linkJump:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_007_linkjump.tree
- V3LinkInc.cpp:363:  linkIncrements:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_008_linkinc.tree
- V3Param.cpp:2111:   param:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_009_param.tree
- V3LinkDot.cpp:5646: linkDotParamed:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_010_linkdotparam.tree
- V3Dead.cpp:602:     deadifyModules:
- V3Width.cpp:9185:   width:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_013_width.tree
- V3WidthCommit.cpp:536:widthCommit:
- V3Const.cpp:4324:   constifyAllLive:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_015_const.tree
- V3Undriven.cpp:572: undrivenAll:
- V3AssertProp.cpp:257:assertPropAll:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_016_assertproperties.tree
- V3AssertPre.cpp:697:assertPreAll:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_017_assertpre.tree
- V3Assert.cpp:962:   assertAll:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_018_assert.tree
- V3LinkLevel.cpp:163:wrapTop:
- V3Const.cpp:4291:   constifyAllLint:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_020_const.tree
- V3SplitVar.cpp:1338:splitVariable:
- V3Inst.cpp:721:     dearrayAll:
- V3LinkDot.cpp:5652: linkDotArrayed:
- V3Begin.cpp:420:    debeginAll:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_025_begin.tree
- V3Tristate.cpp:1934:tristateAll:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_026_tristate.tree
- V3Unknown.cpp:596:  unknownAll:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_027_unknown.tree
- V3DfgOptimizer.cpp:236:extract:
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_028_dfg-extract.tree
- V3DfgOptimizer.cpp:430:optimize:
%Error: Internal Error: ./verilisst_test.sv:12:28: ../V3Dfg.h:355: DfgVertex is not of expected type, but instead has type 'SPLICEPACKED'
   12 |     output t_struct_2      o_data_struct_2
      |                            ^~~~~~~~~~~~~~~
                        ... See the manual at https://verilator.org/verilator_doc.html?v=5.044 for more assistance.
- V3Ast.cpp:1391:     Dumping obj_dir/Vverilisst_test_990_final.tree
- V3StatsReport.cpp:233:statsReport:
%Error: Internal Error: Aborting since under --debug
%Error: export VERILATOR_ROOT=./verilator
%Error: ulimit -s unlimited 2>/dev/null; exec ./verilator_bin_dbg -cc --build -j 8 --threads 1 -MAKEFLAGS libVverilisst_test.a -CFLAGS -fdiagnostics-color=always -CFLAGS -O3 -Wno-lint -Wno-widthconcat -Wno-unoptflat -Wno-timescalemod -Wno-multidriven -Wno-BLKANDNBLK --unroll-count 999999 --unroll-stmts 999999 --structs-packed -CFLAGS -fPIC --no-timing -fno-reloop --debug --prefix Vverilisst_test -f input.vc
%Error: Command Failed ulimit -s unlimited 2>/dev/null; exec ./verilator_bin_dbg -cc --build -j 8 --threads 1 -MAKEFLAGS libVverilisst_test.a -CFLAGS -fdiagnostics-color=always -CFLAGS -O3 -Wno-lint -Wno-widthconcat -Wno-unoptflat -Wno-timescalemod -Wno-multidriven -Wno-BLKANDNBLK --unroll-count 999999 --unroll-stmts 999999 --structs-packed -CFLAGS -fPIC --no-timing -fno-reloop --debug --prefix Vverilisst_test -f input.vc
make: *** [Makefile:27: run] Error 134

I tried rewriting the way these structs are assigned and connected, but none of the attempts were successful — the same error appears in every case.
I’m not sure whether this is a known issue or an actual limitation. Any help or guidance would be greatly appreciated.

Regards.

[gezalore]

Thanks for the report "Internal Error" without any previously reported errors is a bug. I will look into this.

[fede541]

UPDATE:

I removed the --structs-packed flag from the command line and the problem was solved.

I don’t know whether this flag is incompatible with this specific design, or if this is actually a bug.