Example:
module foo(
input logic clk
);
sequence sync_posedge;
@(posedge clk) 1;
endsequence
endmodule
This produces the following error:
$ verilator --lint-only test.sv
%Error: test.sv:6:6: syntax error, unexpected '@', expecting IDENTIFIER-for-type
6 | @(posedge clk) 1;
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=5.049 for more assistance.
%Error: Cannot continue
... This fatal error may be caused by the earlier error(s); resolve those first.
However, I believe this is valid SV and it parses fine under Slang:
$ slang test.sv
Top level design units:
foo
Build succeeded: 0 errors, 0 warnings
Verilator version: Verilator 5.049 devel rev v5.048-44-gd5d799bdd
OS: Arch Linux
Example:
This produces the following error:
However, I believe this is valid SV and it parses fine under Slang:
Verilator version:
Verilator 5.049 devel rev v5.048-44-gd5d799bddOS: Arch Linux