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tangxifantangxifan
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Merge branch 'rr_graph_refactoring' of https://github.com/tangxifan/vtr-verilog-to-routing into rr_graph_refactoring
2 parents 78c4fe0 + fa69111 commit 057ded1

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‎vpr/src/device/rr_graph_obj.cpp

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -714,10 +714,6 @@ bool RRGraph::validate_edge_sink_nodes() const {
714714
* Warnings are thrown if optional checking fails
715715
*/
716716
bool RRGraph::validate() const {
717-
<<<<<<< HEAD
718-
=======
719-
bool check_flag = true;
720-
>>>>>>> 108205c8d... add RRGraph object and basic check_rr_graph_obj() function
721717
size_t num_err = 0;
722718

723719
initialize_fast_node_lookup();
@@ -727,55 +723,32 @@ bool RRGraph::validate() const {
727723
*/
728724
if (false == validate_sizes()) {
729725
VTR_LOG_WARN("Fail in validating node- and edge-related vector sizes!\n");
730-
<<<<<<< HEAD
731-
=======
732-
check_flag = false;
733-
>>>>>>> 108205c8d... add RRGraph object and basic check_rr_graph_obj() function
734726
num_err++;
735727
}
736728

737729
/* Fundamental check */
738730
if (false == validate_nodes_edges()) {
739731
VTR_LOG_WARN("Fail in validating edges connected to each node!\n");
740-
<<<<<<< HEAD
741-
=======
742-
check_flag = false;
743-
>>>>>>> 108205c8d... add RRGraph object and basic check_rr_graph_obj() function
744732
num_err++;
745733
}
746734

747735
if (false == validate_node_segments()) {
748736
VTR_LOG_WARN("Fail in validating segment IDs of nodes !\n");
749-
<<<<<<< HEAD
750-
=======
751-
check_flag = false;
752-
>>>>>>> 108205c8d... add RRGraph object and basic check_rr_graph_obj() function
753737
num_err++;
754738
}
755739

756740
if (false == validate_edge_switches()) {
757741
VTR_LOG_WARN("Fail in validating switch IDs of edges !\n");
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<<<<<<< HEAD
759-
=======
760-
check_flag = false;
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>>>>>>> 108205c8d... add RRGraph object and basic check_rr_graph_obj() function
762742
num_err++;
763743
}
764744

765745
/* Error out if there is any fatal errors found */
766-
<<<<<<< HEAD
767746
if (0 < num_err) {
768747
VTR_LOG_ERROR("Routing Resource graph is not valid due to %d fatal errors !\n",
769748
num_err);
770749
}
771750

772751
return (0 == num_err);
773-
=======
774-
VTR_LOG_ERROR("Routing Resource graph is not valid due to %d fatal errors !\n",
775-
num_err);
776-
777-
return check_flag;
778-
>>>>>>> 108205c8d... add RRGraph object and basic check_rr_graph_obj() function
779752
}
780753

781754
bool RRGraph::is_dirty() const {
@@ -851,10 +824,7 @@ RRNodeId RRGraph::create_node(const t_rr_type& type) {
851824
node_sides_.push_back(NUM_SIDES);
852825
node_Rs_.push_back(0.);
853826
node_Cs_.push_back(0.);
854-
<<<<<<< HEAD
855827
node_segments_.push_back(RRSegmentId::INVALID());
856-
=======
857-
>>>>>>> 108205c8d... add RRGraph object and basic check_rr_graph_obj() function
858828

859829
node_in_edges_.emplace_back(); //Initially empty
860830
node_out_edges_.emplace_back(); //Initially empty

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
1-
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time
2-
k6_N10_mem32K_40nm.xml stereovision3.v common 0.97 0.02 9300 4 0.13 -1 -1 33000 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25448 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 392 0.06 2.2162 -164.467 -2.2162 418 556 1363 148905 22193 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.33587 -171.112 -2.33587 0 0 0.05
3-
k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.22 0.04 9516 5 0.14 -1 -1 33248 -1 -1 14 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 28064 11 30 313 321 2 117 55 7 7 49 clb auto 0.21 380 0.06 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02
1+
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time
2+
k6_N10_mem32K_40nm.xml stereovision3.v common 1.63 0.08 6660 4 0.15 -1 -1 31744 -1 -1 19 11 0 0 465627bf4-dirty success 38220 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 392 0.09 2.2162 -164.467 -2.2162 415 894 2182 196064 29715 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.24204 -171.083 -2.24204 0 0 0.07
3+
k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.85 0.06 6676 5 0.16 -1 -1 32296 -1 -1 14 11 0 0 465627bf4-dirty success 44644 11 30 313 321 2 117 55 7 7 49 clb auto 0.34 380 0.08 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
2-
k4_n4_v7_bidir.xml styr.blif common 0.95 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21744 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1261 0.12 5.33383 -68.3994 -5.33383 16 1903 29 2.43e+06 2.01e+06 -1 -1 0.48 1826 16 939 2863 195365 30983 7.17859 -89.6405 -7.17859 0 0 -1 -1 0.06
3-
k4_n4_v7_longline_bidir.xml styr.blif common 0.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21888 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1211 0.18 6.07334 -70.9644 -6.07334 18 2324 21 2.43e+06 2.01e+06 -1 -1 0.25 2262 45 1271 3738 304440 42218 8.37849 -101.759 -8.37849 0 0 -1 -1 0.07
4-
k4_n4_v7_l1_bidir.xml styr.blif common 1.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22404 10 10 253 263 1 169 87 11 11 121 clb auto 0.04 1227 0.12 6.05408 -74.8187 -6.05408 10 1522 37 2.43e+06 2.01e+06 -1 -1 1.07 1214 16 1112 3531 274215 52624 7.44659 -87.7658 -7.44659 0 0 -1 -1 0.05
5-
k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21504 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1236 0.33 5.30313 -63.535 -5.30313 16 2042 28 2.43e+06 2.01e+06 -1 -1 0.59 1979 19 1142 3366 494089 68283 7.86978 -98.8292 -7.86978 0 0 -1 -1 0.07
1+
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time
2+
k4_n4_v7_bidir.xml styr.blif common 1.67 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 465627bf4-dirty success 27996 10 10 253 263 1 169 87 11 11 121 clb auto 0.07 1261 0.20 5.33383 -68.3994 -5.33383 14 2173 40 2.43e+06 2.01e+06 -1 -1 0.72 1871 22 1384 4179 321517 48548 7.73456 -97.2593 -7.73456 0 0 -1 -1 0.09
3+
k4_n4_v7_longline_bidir.xml styr.blif common 1.36 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 465627bf4-dirty success 27040 10 10 253 263 1 169 87 11 11 121 clb auto 0.06 1211 0.20 6.07334 -70.9644 -6.07334 18 2323 23 2.43e+06 2.01e+06 -1 -1 0.47 2322 33 1620 4721 399237 52574 8.83208 -104.624 -8.83208 0 0 -1 -1 0.10
4+
k4_n4_v7_l1_bidir.xml styr.blif common 1.96 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 465627bf4-dirty success 34040 10 10 253 263 1 169 87 11 11 121 clb auto 0.06 1227 0.22 6.05408 -74.8187 -6.05408 11 1536 30 2.43e+06 2.01e+06 -1 -1 1.01 1223 17 1178 3755 295929 56473 7.86559 -90.249 -7.86559 0 0 -1 -1 0.06
5+
k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 465627bf4-dirty success 27976 10 10 253 263 1 169 87 11 11 121 clb auto 0.08 1236 0.40 5.30313 -63.535 -5.30313 17 2135 34 2.43e+06 2.01e+06 -1 -1 0.92 2086 22 1325 4110 738933 96241 13.0859 -137.078 -13.0859 0 0 -1 -1 0.14

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