made a few function operating on t_pb_type its member functions

Author: soheilshahrouz

libs/libarchfpga/src/physical_types.cpp

@@ -252,7 +252,71 @@ const t_port* t_logical_block_type::get_port_by_pin(int pin) const {
     return nullptr;
 }
 
-/**
+/*
+ * t_pb_type
+ */
+
+int t_pb_type::get_max_primitives() const {
+    int max_size;
+
+    if (modes == nullptr) {
+        max_size = 1;
+    } else {
+        max_size = 0;
+        int temp_size = 0;
+        for (int i = 0; i < num_modes; i++) {
+            for (int j = 0; j < modes[i].num_pb_type_children; j++) {
+                temp_size += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_primitives();
+            }
+            if (temp_size > max_size) {
+                max_size = temp_size;
+            }
+        }
+    }
+
+    return max_size;
+}
+
+/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */
+int t_pb_type::get_max_nets() const {
+    int max_nets;
+    if (modes == nullptr) {
+        max_nets = num_output_pins;
+    } else {
+        max_nets = 0;
+
+        for (int i = 0; i < num_modes; i++) {
+            int temp_nets = 0;
+            for (int j = 0; j < modes[i].num_pb_type_children; j++) {
+                temp_nets += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_nets();
+            }
+
+            if (temp_nets > max_nets) {
+                max_nets = temp_nets;
+            }
+        }
+    }
+
+    if (is_root()) {
+        max_nets += num_input_pins + num_output_pins + num_clock_pins;
+    }
+
+    return max_nets;
+}
+
+int t_pb_type::get_max_depth() const {
+    int max_depth = depth;
+
+    for (int i = 0; i < num_modes; i++) {
+        for (int j = 0; j < modes[i].num_pb_type_children; j++) {
+            int temp_depth = modes[i].pb_type_children[j].get_max_depth();
+            max_depth = std::max(max_depth, temp_depth);
+        }
+    }
+    return max_depth;
+}
+
+/*
  * t_pb_graph_node
  */
 

libs/libarchfpga/src/physical_types.h

@@ -1092,6 +1092,10 @@ struct t_pb_type {
     inline bool is_primitive() const {
         return num_modes == 0;
     }
+
+    int get_max_primitives() const;
+    int get_max_depth() const;
+    int get_max_nets() const;
 };
 
 /** Describes an operational mode of a clustered logic block

vpr/src/util/vpr_utils.cpp

@@ -729,66 +729,6 @@ static bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::reg
     return false;
 }
 
-int get_max_primitives_in_pb_type(t_pb_type* pb_type) {
-    int max_size;
-    if (pb_type->modes == nullptr) {
-        max_size = 1;
-    } else {
-        max_size = 0;
-        int temp_size = 0;
-        for (int i = 0; i < pb_type->num_modes; i++) {
-            for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
-                temp_size += pb_type->modes[i].pb_type_children[j].num_pb
-                             * get_max_primitives_in_pb_type(
-                                 &pb_type->modes[i].pb_type_children[j]);
-            }
-            if (temp_size > max_size) {
-                max_size = temp_size;
-            }
-        }
-    }
-    return max_size;
-}
-
-/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */
-int get_max_nets_in_pb_type(const t_pb_type* pb_type) {
-    int max_nets;
-    if (pb_type->modes == nullptr) {
-        max_nets = pb_type->num_output_pins;
-    } else {
-        max_nets = 0;
-        for (int i = 0; i < pb_type->num_modes; i++) {
-            int temp_nets = 0;
-            for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
-                temp_nets += pb_type->modes[i].pb_type_children[j].num_pb
-                             * get_max_nets_in_pb_type(
-                                 &pb_type->modes[i].pb_type_children[j]);
-            }
-            if (temp_nets > max_nets) {
-                max_nets = temp_nets;
-            }
-        }
-    }
-    if (pb_type->is_root()) {
-        max_nets += pb_type->num_input_pins + pb_type->num_output_pins
-                    + pb_type->num_clock_pins;
-    }
-    return max_nets;
-}
-
-int get_max_depth_of_pb_type(t_pb_type* pb_type) {
-    int max_depth = pb_type->depth;
-    for (int i = 0; i < pb_type->num_modes; i++) {
-        for (int j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
-            int temp_depth = get_max_depth_of_pb_type(&pb_type->modes[i].pb_type_children[j]);
-            if (temp_depth > max_depth) {
-                max_depth = temp_depth;
-            }
-        }
-    }
-    return max_depth;
-}
-
 /**
  * given an atom block and physical primitive type, is the mapping legal
  */

vpr/src/util/vpr_utils.h

@@ -180,9 +180,6 @@ InstPort parse_inst_port(const std::string& str);
 //Returns the block type which is most likely the logic block
 t_logical_block_type_ptr infer_logic_block_type(const DeviceGrid& grid);
 
-int get_max_primitives_in_pb_type(t_pb_type* pb_type);
-int get_max_depth_of_pb_type(t_pb_type* pb_type);
-int get_max_nets_in_pb_type(const t_pb_type* pb_type);
 bool primitive_type_feasible(AtomBlockId blk_id, const t_pb_type* cur_pb_type);
 t_pb_graph_pin* get_pb_graph_node_pin_from_model_port_pin(const t_model_ports* model_port, const int model_pin, const t_pb_graph_node* pb_graph_node);
 /// @brief Gets the pb_graph_node pin at the given pin index for the given