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author
djns1
committed
Implemented InOuts
1 parent 9108b17 commit 3d55dc4

19 files changed

+302
-181
lines changed

‎ODIN_II/SRC/ast_elaborate.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2656,11 +2656,11 @@ void create_param_table_for_scope(ast_node_t* module_items, sc_hierarchy* local_
26562656
/* symbols are already dealt with */
26572657
if (var_declare->types.variable.is_input
26582658
|| var_declare->types.variable.is_output
2659+
|| var_declare->types.variable.is_inout
26592660
|| var_declare->types.variable.is_reg
26602661
|| var_declare->types.variable.is_genvar
26612662
|| var_declare->types.variable.is_wire
26622663
|| var_declare->types.variable.is_defparam)
2663-
26642664
continue;
26652665

26662666
oassert(module_items->children[i]->children[j]->type == VAR_DECLARE);

‎ODIN_II/SRC/netlist_create_from_ast.cpp

Lines changed: 71 additions & 61 deletions
Large diffs are not rendered by default.

‎ODIN_II/SRC/netlist_utils.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -296,7 +296,8 @@ nnet_t* allocate_nnet() {
296296
*-------------------------------------------------------------------------------------------*/
297297
nnet_t* free_nnet(nnet_t* to_free) {
298298
if (to_free) {
299-
to_free->fanout_pins = (npin_t**)vtr::free(to_free->fanout_pins);
299+
if (to_free->num_fanout_pins)
300+
to_free->fanout_pins = (npin_t**)vtr::free(to_free->fanout_pins);
300301

301302
if (to_free->name)
302303
vtr::free(to_free->name);

‎ODIN_II/SRC/output_blif.cpp

Lines changed: 24 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -65,25 +65,24 @@ static bool warn_undriven(nnode_t* node, nnet_t* net) {
6565
return false;
6666
}
6767

68-
// TODO Uncomment this for In Outs
69-
//static void merge_with_inputs(nnode_t* node, long pin_idx) {
70-
// oassert(pin_idx < node->num_input_pins);
71-
// nnet_t* net = node->input_pins[pin_idx]->net;
72-
// warn_undriven(node, net);
73-
// // Merge node with all inputs with fanout of 1
74-
// if (net->num_fanout_pins <= 1) {
75-
// for (int i = 0; i < net->num_driver_pins; i++) {
76-
// npin_t* driver = net->driver_pins[i];
77-
// if (driver->name != NULL && ((driver->node->type == MULTIPLY) || (driver->node->type == HARD_IP) || (driver->node->type == MEMORY) || (driver->node->type == ADD) || (driver->node->type == MINUS))) {
78-
// vtr::free(driver->name);
79-
// driver->name = vtr::strdup(node->name);
80-
// } else {
81-
// vtr::free(driver->node->name);
82-
// driver->node->name = vtr::strdup(node->name);
83-
// }
84-
// }
85-
// }
86-
//}
68+
static void merge_with_inputs(nnode_t* node, long pin_idx) {
69+
oassert(pin_idx < node->num_input_pins);
70+
nnet_t* net = node->input_pins[pin_idx]->net;
71+
warn_undriven(node, net);
72+
// Merge node with all inputs with fanout of 1
73+
if (net->num_fanout_pins <= 1) {
74+
for (int i = 0; i < net->num_driver_pins; i++) {
75+
npin_t* driver = net->driver_pins[i];
76+
if (driver->name != NULL && ((driver->node->type == MULTIPLY) || (driver->node->type == HARD_IP) || (driver->node->type == MEMORY) || (driver->node->type == ADD) || (driver->node->type == MINUS))) {
77+
vtr::free(driver->name);
78+
driver->name = vtr::strdup(node->name);
79+
} else {
80+
vtr::free(driver->node->name);
81+
driver->node->name = vtr::strdup(node->name);
82+
}
83+
}
84+
}
85+
}
8786

8887
static void print_net_driver(FILE* out, nnode_t* node, nnet_t* net, long driver_idx) {
8988
oassert(driver_idx < net->num_driver_pins);
@@ -221,14 +220,13 @@ void output_blif(FILE* out, netlist_t* netlist) {
221220
fprintf(out, "\n.names gnd\n.names unconn\n.names vcc\n1\n");
222221
fprintf(out, "\n");
223222

224-
// TODO Uncomment this for In Outs
225223
// connect all the outputs up to the last gate
226-
// for (long i = 0; i < netlist->num_top_output_nodes; i++) {
227-
// nnode_t* node = netlist->top_output_nodes[i];
228-
// for (int j = 0; j < node->num_input_pins; j++) {
229-
// merge_with_inputs(node, j);
230-
// }
231-
// }
224+
for (long i = 0; i < netlist->num_top_output_nodes; i++) {
225+
nnode_t* node = netlist->top_output_nodes[i];
226+
for (int j = 0; j < node->num_input_pins; j++) {
227+
merge_with_inputs(node, j);
228+
}
229+
}
232230

233231
/* traverse the internals of the flat net-list */
234232
if (strcmp(configuration.output_type.c_str(), "blif") == 0) {

‎ODIN_II/SRC/parse_making_ast.cpp

Lines changed: 81 additions & 52 deletions
Large diffs are not rendered by default.

‎ODIN_II/regression_test/benchmark/task/syntax/task.conf

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
1616
circuits_dir=regression_test/benchmark/verilog/
1717

1818
circuit_list_add=syntax/*.v
19+
circuit_list_add=syntax/inout-syntax/*.v
1920

2021
synthesis_parse_file=regression_test/parse_result/conf/synth.toml
2122
simulation_parse_file=regression_test/parse_result/conf/sim.toml

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout.v

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
module simple_op(in_out1,in_out2,en);
2+
inout in_out1;
3+
inout in_out2;
4+
input en;
5+
6+
assign in_out1 = (en) ? in_out2 : 1'bz;
7+
assign in_out2 = (!en) ? in_out1 : 1'bz;
8+
endmodule

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout_input

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
GLOBAL_SIM_BASE_CLK en in_out1 in_out2
2+
0 1 z z
3+
1 0 z z
4+
0 1 z 0
5+
1 1 z 1
6+
0 0 1 z
7+
1 0 0 z

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout_output

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
in_out1 in_out2
2+
0 0
3+
1 1
4+
0 0
5+
0 x
6+
1 1
7+
x 1

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic.v

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
module inout_basic(input dir, inout io, output out);
2+
assign io = (dir) ? dir : 1'bz;
3+
assign out = (!dir) ? io : 1'bx;
4+
endmodule

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_input

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
GLOBAL_SIM_BASE_CLK dir io
2+
0 1 0
3+
0 1 0
4+
0 1 1
5+
0 1 1
6+
0 0 0
7+
0 0 0
8+
0 0 1
9+
0 0 1

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_output

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
io out
2+
1 x
3+
1 x
4+
1 x
5+
1 x
6+
0 0
7+
0 0
8+
1 1
9+
1 1

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_input_only.v

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
module inout_assign(inout a, output b);
2+
assign b = a;
3+
endmodule
4+
5+
module inout_basic(input a, output b);
6+
inout_assign c(a, b);
7+
endmodule

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_input_only_input

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
GLOBAL_SIM_BASE_CLK a
2+
0 0
3+
0 1
4+
0 1
5+
0 0
6+
0 1

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_input_only_output

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
b
2+
0
3+
1
4+
1
5+
0
6+
1

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_output_only.v

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
module inout_assign(input a, inout b);
2+
assign b = a;
3+
endmodule
4+
5+
module inout_basic(input a, output b);
6+
inout_assign c(a, b);
7+
endmodule

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_output_only_input

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
GLOBAL_SIM_BASE_CLK a
2+
0 0
3+
0 1
4+
0 1
5+
0 0
6+
0 1

‎ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_output_only_output

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
b
2+
0
3+
1
4+
1
5+
0
6+
1

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