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djns1
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Updated golden results
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‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt

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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.08 0.14 116128 4 0.19 -1 -1 33812 -1 -1 72 99 1 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/ch_intrinsics.v/common 76844 99 130 378 508 1 260 302 13 13 169 clb auto 0.06 638 0.59 0.00 34 1605 10 3.33e+06 2.28e+06 450788. 2667.39 0.68
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k4_N10_memSize16384_memData64.xml diffeq1.v common 8.00 0.10 102712 23 0.23 -1 -1 34256 -1 -1 72 162 0 5 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/diffeq1.v/common 80952 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.21 4324 1.76 0.01 50 10008 26 3.33e+06 2.61e+06 641417. 3795.37 3.79
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k4_N10_memSize16384_memData64.xml single_wire.v common 0.54 0.06 82948 1 0.00 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/single_wire.v/common 67096 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 6 4 1 30000 0 1761.23 195.692 0.01
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k4_N10_memSize16384_memData64.xml single_ff.v common 0.57 0.06 83024 1 0.00 -1 -1 29516 -1 -1 1 2 0 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/single_ff.v/common 67756 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 18 4 1 30000 30000 3112.78 345.864 0.01
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
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k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 11.75 0.03 8932 4 0.21 -1 -1 40008 -1 -1 72 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/ch_intrinsics.v/common 26652 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 638 0.28 0.00 38 1530 9 3.33e+06 2.28e+06 504671. 2986.22 0.35
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k4_N10_memSize16384_memData64.xml diffeq1.v common 14.27 0.02 8644 23 0.28 -1 -1 38212 -1 -1 72 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/diffeq1.v/common 31148 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.16 4324 0.62 0.00 50 10008 26 3.33e+06 2.61e+06 641417. 3795.37 2.02
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k4_N10_memSize16384_memData64.xml single_wire.v common 10.67 0.01 5380 1 0.01 -1 -1 33052 -1 -1 0 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/single_wire.v/common 21184 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
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k4_N10_memSize16384_memData64.xml single_ff.v common 10.66 0.01 5344 1 0.00 -1 -1 33384 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/single_ff.v/common 21308 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 16 9 1 30000 30000 2550.78 283.420 0.00

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