Eves bms

Author: djns1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout.v

@@ -0,0 +1,8 @@
+module simple_op(in_out1,in_out2,en);
+	inout in_out1;
+	inout in_out2;
+	input  en;
+
+	assign in_out1 = (en) ? in_out2 : 1'b1;
+	assign in_out2 = (!en) ? in_out1 : 1'b0;
+endmodule 

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout_input

@@ -0,0 +1,7 @@
+GLOBAL_SIM_BASE_CLK en in_out1 in_out2
+0 1 z z
+1 0 z z
+0 1 z 0
+1 1 z 1
+0 0 1 z
+1 0 0 z

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/double_assign_inout_output

@@ -0,0 +1,7 @@
+in_out1 in_out2
+0 0
+1 1
+0 0
+0 x
+1 1
+x 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic.v

@@ -1,17 +1,15 @@
-module selector(input sel, input in, output out, inout io);
-    // Select if selector is set
-    assign io = (sel) ? in : 1'bz;
-    assign out = io;
-endmodule
+//module selector(input sel, input in, inout io);
+//    // Select if selector is set
+//    assign io = (sel) ? in : 1'bz;
+//endmodule
 
 module inout_basic(input line_sel, input in1, input in2, output out);
-    tri internal;
-    tri wip;
+    wire internal;
     wire not_sel;
     assign not_sel = !line_sel;
-    // Select in1 if oe
-    selector s1( line_sel, in1, wip, internal, internal );
-    // Selects in2 if !oe
-    selector s2( not_sel, in2, wip, internal, internal );
-    assign out = wip;
+    // Select in1 if line_sel
+    selector s1( line_sel, in1, internal );
+    // Selects in2 if !line_sel
+    selector s2( not_sel, in2, internal );
+    assign out = internal;
 endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_failure.v

@@ -0,0 +1,11 @@
+
+module simple_op(in,in_out1,in_out2,en,out);
+	input  in;
+	inout reg in_out1;
+	inout reg in_out2;
+	input  en;
+	output out;
+	
+	assign in_out1 = (en) ? in : 1'bz;
+	assign out = in_out2;
+endmodule 

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_manual_impl.v

@@ -5,13 +5,12 @@ module selector_manual(input sel, input in, output out, input io_in, output io_o
 endmodule
 
 module inout_manual(input line_sel, input in1, input in2, output out);
-    tri internal;
-    tri wip;
+    wire internal;
     wire not_sel;
     assign not_sel = !line_sel;
     // Select in1 if oe
-    selector_manual s1( line_sel, in1, wip, internal, internal );
+    selector_manual s1( line_sel, in1, internal, internal );
     // Selects in2 if !oe
-    selector_manual s2( not_sel, in2, wip, internal, internal );
-    assign out = wip;
+    selector_manual s2( not_sel, in2, internal, internal );
+    assign out = internal;
 endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/simple_inout.v

@@ -0,0 +1,10 @@
+module simple_op(in,in_out1,in_out2,en,out);
+	input  in;
+	inout wire in_out1;
+	inout wire in_out2;
+	input  en;
+	output out;
+	
+	assign in_out1 = (en) ? in : 1'bz;
+	assign out = in_out2;
+endmodule 

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/simple_inout_input

@@ -0,0 +1,4 @@
+GLOBAL_SIM_BASE_CLK en in in_out2
+0 0 1 1
+0 1 0 0
+0 1 1 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/simple_inout_output

@@ -0,0 +1,4 @@
+in_out2 out
+z 1
+0 0
+1 1