Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into openfpga_update

Author: amin1377

CMakeLists.txt

@@ -43,9 +43,6 @@ option(VTR_ENABLE_CAPNPROTO "Enable capnproto binary serialization support in VP
 #Allow the user to decide whether to compile the server module
 option(VPR_USE_SERVER "Specify whether vpr enables the server mode" ON)
 
-#Allow the user to enable/disable VPR analytic placement
-#VPR option --enable_analytic_placer is also required for Analytic Placement
-option(VPR_ANALYTIC_PLACE "Enable analytic placement in VPR." ON)
 option(VPR_ENABLE_INTERCHANGE "Enable FPGA interchange." ON)
 option(VPR_ENABLE_NOC_SAT_ROUTING "Enable NoC SAT routing." OFF)
 

libs/libarchfpga/src/physical_types.cpp

@@ -252,7 +252,71 @@ const t_port* t_logical_block_type::get_port_by_pin(int pin) const {
     return nullptr;
 }
 
-/**
+/*
+ * t_pb_type
+ */
+
+int t_pb_type::get_max_primitives() const {
+    int max_size;
+
+    if (modes == nullptr) {
+        max_size = 1;
+    } else {
+        max_size = 0;
+        int temp_size = 0;
+        for (int i = 0; i < num_modes; i++) {
+            for (int j = 0; j < modes[i].num_pb_type_children; j++) {
+                temp_size += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_primitives();
+            }
+            if (temp_size > max_size) {
+                max_size = temp_size;
+            }
+        }
+    }
+
+    return max_size;
+}
+
+/* finds maximum number of nets that can be contained in pb_type, this is bounded by the number of driving pins */
+int t_pb_type::get_max_nets() const {
+    int max_nets;
+    if (modes == nullptr) {
+        max_nets = num_output_pins;
+    } else {
+        max_nets = 0;
+
+        for (int i = 0; i < num_modes; i++) {
+            int temp_nets = 0;
+            for (int j = 0; j < modes[i].num_pb_type_children; j++) {
+                temp_nets += modes[i].pb_type_children[j].num_pb * modes[i].pb_type_children[j].get_max_nets();
+            }
+
+            if (temp_nets > max_nets) {
+                max_nets = temp_nets;
+            }
+        }
+    }
+
+    if (is_root()) {
+        max_nets += num_input_pins + num_output_pins + num_clock_pins;
+    }
+
+    return max_nets;
+}
+
+int t_pb_type::get_max_depth() const {
+    int max_depth = depth;
+
+    for (int i = 0; i < num_modes; i++) {
+        for (int j = 0; j < modes[i].num_pb_type_children; j++) {
+            int temp_depth = modes[i].pb_type_children[j].get_max_depth();
+            max_depth = std::max(max_depth, temp_depth);
+        }
+    }
+    return max_depth;
+}
+
+/*
  * t_pb_graph_node
  */
 

libs/libarchfpga/src/physical_types.h

@@ -730,6 +730,11 @@ struct t_physical_tile_type {
     ///@brief Is this t_physical_tile_type an empty type?
     bool is_empty() const;
 
+    ///@brief Returns true if the physical tile type can implement either a .input or .output block type
+    inline bool is_io() const {
+        return is_input_type || is_output_type;
+    }
+
     ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port
     int find_pin(std::string_view port_name, int pin_index_in_port) const;
 
@@ -1092,6 +1097,10 @@ struct t_pb_type {
     inline bool is_primitive() const {
         return num_modes == 0;
     }
+
+    int get_max_primitives() const;
+    int get_max_depth() const;
+    int get_max_nets() const;
 };
 
 /** Describes an operational mode of a clustered logic block

libs/libarchfpga/src/physical_types_util.cpp

@@ -637,21 +637,6 @@ bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from
     return false;
 }
 
-// TODO: Remove is_input_type / is_output_type / is_io_type as part of
-// https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1193
-bool is_input_type(t_physical_tile_type_ptr type) {
-    return type->is_input_type;
-}
-
-bool is_output_type(t_physical_tile_type_ptr type) {
-    return type->is_output_type;
-}
-
-bool is_io_type(t_physical_tile_type_ptr type) {
-    return is_input_type(type)
-           || is_output_type(type);
-}
-
 std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_physical_num, bool is_flat) {
     int max_ptc = get_tile_pin_max_ptc(type, is_flat);
     VTR_ASSERT(pin_physical_num < max_ptc);

libs/libarchfpga/src/physical_types_util.h

@@ -120,13 +120,6 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type);
 ///@brief Returns true if the specified pin is located at "from_layer" and it is connected to "to_layer"
 bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, int num_of_avail_layer);
 
-///@brief Returns true if the given physical tile type can implement a .input block type
-bool is_input_type(t_physical_tile_type_ptr type);
-///@brief Returns true if the given physical tile type can implement a .output block type
-bool is_output_type(t_physical_tile_type_ptr type);
-///@brief Returns true if the given physical tile type can implement either a .input or .output block type
-bool is_io_type(t_physical_tile_type_ptr type);
-
 /**
  * @brief Returns the corresponding physical pin based on the input parameters:
  *

vpr/CMakeLists.txt

@@ -91,21 +91,6 @@ else ()
     message(STATUS "Eigen3: Not Found. Some features may be disabled.")
 endif (TARGET Eigen3::Eigen)
 
-#VPR_ANALYTIC_PLACE is initialized in the root CMakeLists
-# NOTE: This is the cluster-level Analytical Placement which existed before the
-#       flat Analytical Placement flow.
-if(${VPR_ANALYTIC_PLACE})
-	message(STATUS "VPR Analytic Placement: Requested")
-	if (TARGET Eigen3::Eigen)
-		message(STATUS "VPR Analytic Placement dependency (Eigen3): Found")
-		message(STATUS "VPR Analytic Placement: Enabled")
-		target_compile_definitions(libvpr PUBLIC -DENABLE_ANALYTIC_PLACE)
-	else ()
-		message(STATUS "VPR Analytic Placement dependency (Eigen3): Not Found (Download manually with sudo apt install libeigen3-dev, and rebuild)")
-		message(STATUS "VPR Analytic Placement: Disabled")
-	endif(TARGET Eigen3::Eigen)
-endif()
-
 if (${VPR_ENABLE_NOC_SAT_ROUTING})
     message(STATUS "VPR NoC SAT Routing: Requested")
     find_package(ortools CONFIG REQUIRED)

vpr/src/base/SetupVPR.cpp

@@ -701,7 +701,6 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts)
 
     PlacerOpts->effort_scaling = Options.place_effort_scaling;
     PlacerOpts->timing_update_type = Options.timing_update_type;
-    PlacerOpts->enable_analytic_placer = Options.enable_analytic_placer;
     PlacerOpts->place_static_move_prob = vtr::vector<e_move_type, float>(Options.place_static_move_prob.value().begin(),
                                                                          Options.place_static_move_prob.value().end());
     PlacerOpts->place_high_fanout_net = Options.place_high_fanout_net;

vpr/src/base/ShowSetup.cpp

@@ -135,7 +135,7 @@ ClusteredNetlistStats::ClusteredNetlistStats() {
         auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
         auto physical_tile = pick_physical_type(logical_block);
         num_blocks_type[logical_block->index]++;
-        if (is_io_type(physical_tile)) {
+        if (physical_tile->is_io()) {
             for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
                 int physical_pin = get_physical_pin(physical_tile, logical_block, j);
 

vpr/src/base/check_netlist.cpp

@@ -110,8 +110,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
         int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id);
         int pin_index = get_physical_pin(physical_type, logical_type, log_index);
 
-        if (physical_type->is_ignored_pin[pin_index] != net_is_ignored
-            && !is_io_type(physical_type)) {
+        if (physical_type->is_ignored_pin[pin_index] != net_is_ignored && !physical_type->is_io()) {
             VTR_LOGV_WARN(verbosity > 2,
                           "Global net '%s' connects to non-global architecture pin '%s' (netlist pin '%s')\n",
                           cluster_ctx.clb_nlist.net_name(net_id).c_str(),

vpr/src/base/read_options.cpp

@@ -2244,13 +2244,6 @@ argparse::ArgumentParser create_arg_parser(const std::string& prog_name, t_optio
         .default_value("0")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
-    place_grp.add_argument(args.enable_analytic_placer, "--enable_analytic_placer")
-        .help(
-            "Enables the analytic placer. "
-            "Once analytic placement is done, the result is passed through the quench phase of the annealing placer for local improvement")
-        .default_value("false")
-        .show_in(argparse::ShowIn::HELP_ONLY);
-
     place_grp.add_argument(args.place_static_move_prob, "--place_static_move_prob")
         .help(
             "The percentage probabilities of different moves in Simulated Annealing placement. "

vpr/src/base/read_options.h

@@ -139,7 +139,6 @@ struct t_options {
     argparse::ArgValue<int> placement_saves_per_temperature;
     argparse::ArgValue<e_place_effort_scaling> place_effort_scaling;
     argparse::ArgValue<e_place_delta_delay_algorithm> place_delta_delay_matrix_calculation_method;
-    argparse::ArgValue<bool> enable_analytic_placer;
     argparse::ArgValue<std::vector<float>> place_static_move_prob;
     argparse::ArgValue<int> place_high_fanout_net;
     argparse::ArgValue<e_place_bounding_box_mode> place_bounding_box_mode;

vpr/src/base/read_route.cpp

@@ -296,7 +296,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN
             /* Verify types and ptc*/
             if (tokens[2] == "SOURCE" || tokens[2] == "SINK" || tokens[2] == "OPIN" || tokens[2] == "IPIN") {
                 const auto& type = device_ctx.grid.get_physical_type({x, y, layer_num});
-                if (tokens[4 + offset] == "Pad:" && !is_io_type(type)) {
+                if (tokens[4 + offset] == "Pad:" && !type->is_io()) {
                     vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                               "Node %d is of the wrong type", inode);
                 }
@@ -319,7 +319,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN
             if (tokens[6 + offset] != "Switch:") {
                 /*This is an opin or ipin, process its pin nums*/
                 auto type = device_ctx.grid.get_physical_type({x, y, layer_num});
-                if (!is_io_type(type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) {
+                if (!type->is_io() && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) {
                     int pin_num = rr_graph.node_pin_num(RRNodeId(inode));
                     int width_offset = device_ctx.grid.get_width_offset({x, y, layer_num});
                     int height_offset = device_ctx.grid.get_height_offset({x, y, layer_num});
@@ -592,10 +592,13 @@ void print_route(const Netlist<>& net_list,
                         fprintf(fp, "to (%d,%d,%d) ", rr_graph.node_xhigh(inode),
                                 rr_graph.node_yhigh(inode), layer_num);
 
+                    t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num});
+
                     switch (rr_type) {
                         case e_rr_type::IPIN:
                         case e_rr_type::OPIN:
-                            if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) {
+
+                            if (physical_tile->is_io()) {
                                 fprintf(fp, " Pad: ");
                             } else { /* IO Pad. */
                                 fprintf(fp, " Pin: ");
@@ -609,7 +612,7 @@ void print_route(const Netlist<>& net_list,
 
                         case e_rr_type::SOURCE:
                         case e_rr_type::SINK:
-                            if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) {
+                            if (physical_tile->is_io()) {
                                 fprintf(fp, " Pad: ");
                             } else { /* IO Pad. */
                                 fprintf(fp, " Class: ");
@@ -629,8 +632,7 @@ void print_route(const Netlist<>& net_list,
 
                     fprintf(fp, "%d  ", rr_graph.node_ptc_num(inode));
 
-                    auto physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num});
-                    if (!is_io_type(physical_tile) && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) {
+                    if (!physical_tile->is_io() && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) {
                         int pin_num = rr_graph.node_pin_num(inode);
                         int xoffset = device_ctx.grid.get_width_offset({ilow, jlow, layer_num});
                         int yoffset = device_ctx.grid.get_height_offset({ilow, jlow, layer_num});

vpr/src/base/stats.cpp

@@ -91,10 +91,7 @@ void routing_stats(const Netlist<>& net_list,
                 auto type = device_ctx.grid.get_physical_type({i, j, layer_num});
                 int width_offset = device_ctx.grid.get_width_offset({i, j, layer_num});
                 int height_offset = device_ctx.grid.get_height_offset({i, j, layer_num});
-                if (width_offset == 0
-                    && height_offset == 0
-                    && !is_io_type(type)
-                    && type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) {
+                if (width_offset == 0 && height_offset == 0 && !type->is_io() && !type->is_empty()) {
                     if (type->area == UNDEFINED) {
                         area += grid_logic_tile_area * type->width * type->height;
                     } else {
@@ -111,7 +108,7 @@ void routing_stats(const Netlist<>& net_list,
     for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) {
         t_pl_loc block_loc = block_locs[blk_id].loc;
         auto type = physical_tile_type(block_loc);
-        if (!is_io_type(type)) {
+        if (!type->is_io()) {
             if (type->area == UNDEFINED) {
                 used_area += grid_logic_tile_area * type->width * type->height;
             } else {
@@ -473,7 +470,7 @@ void print_lambda() {
         t_pl_loc block_loc = block_locs[blk_id].loc;
         auto type = physical_tile_type(block_loc);
         VTR_ASSERT(type != nullptr);
-        if (!is_io_type(type)) {
+        if (!type->is_io()) {
             for (int ipin = 0; ipin < type->num_pins; ipin++) {
                 if (get_pin_type_from_pin_physical_num(type, ipin) == RECEIVER) {
                     ClusterNetId net_id = cluster_ctx.clb_nlist.block_net(blk_id, ipin);

vpr/src/base/vpr_types.h

@@ -1071,14 +1071,6 @@ struct t_placer_opts {
     std::string allowed_tiles_for_delay_model;
 
     e_place_delta_delay_algorithm place_delta_delay_matrix_calculation_method;
-
-    /*
-     * @brief enables the analytic placer.
-     *
-     * Once analytic placement is done, the result is passed through the quench phase
-     * of the annealing placer for local improvement
-     */
-    bool enable_analytic_placer;
 };
 
 /******************************************************************

vpr/src/pack/appack_max_dist_th_manager.cpp

@@ -100,7 +100,7 @@ void APPackMaxDistThManager::auto_set_max_distance_thresholds(const std::vector<
         // Find which type(s) this logical block type looks like.
         bool has_memory = has_memory_pbs(lb_ty.pb_type);
         bool is_logic_block_type = (lb_ty.index == logic_block_type->index);
-        bool is_io_block = is_io_type(pick_physical_type(&lb_ty));
+        bool is_io_block = pick_physical_type(&lb_ty)->is_io();
 
         // Update the max distance threshold based on the type. If the logical
         // block type looks like many block types at the same time (for example