Added 'manual' implementation of inout to test behaviour

Author: djns1

ODIN_II/SRC/parse_making_ast.cpp

@@ -1928,9 +1928,10 @@ void graphVizOutputAst_traverse_node(FILE* fp, ast_node_t* node, ast_node_t* fro
     switch (node->type) {
         case VAR_DECLARE: {
             std::stringstream temp;
-            if (node->types.variable.is_input) temp << " INPUT";
-            if (node->types.variable.is_output) temp << " OUTPUT";
             if (node->types.variable.is_inout) temp << " INOUT";
+            else if (node->types.variable.is_input) temp << " INPUT";
+            else if (node->types.variable.is_output) temp << " OUTPUT";
+            
             if (node->types.variable.is_port) temp << " PORT";
             if (node->types.variable.is_parameter) temp << " PARAMETER";
             if (node->types.variable.is_wire) temp << " WIRE";

ODIN_II/exec_wrapper.sh

@@ -175,12 +175,13 @@ function display() {
 	esac
 
 	# check for uncaught errors
-
 	ERROR_CATCH="$(cat "${LOG_FILE}" | grep 'Odin exited with code: ' | awk '{print $5}' | grep -E '^\-?[0-9]+$')"
 	[ "_${ERROR_CATCH}" != "_" ] && EXIT_CODE="${ERROR_CATCH}"
 
 	EXIT_ERROR_TYPE=$( print_exit_type "${EXIT_CODE}" )
 
+	MISMATCH_CHECK="$(cat "${LOG_FILE}" | grep "Error::OUTPUT_BLIF Vector files differ.")"
+	[ "_${MISMATCH_CHECK}" != "_" ] && EXIT_ERROR_TYPE="MISMATCH"
 
 	if [ "_${EXIT_CODE}" == "_0" ] && [ "_${LEAK_MESSAGE}" == "_" ]
 	then

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic.v

@@ -1,12 +1,17 @@
-module inout_reg(input oe, inout line);
-    reg val;
-    assign line = oe ? val : 1'bz;
-    assign val = oe ? 1'bz : line;
+module selector(input sel, input in, output out, inout io);
+    // Select if selector is set
+    assign io = (sel) ? in : 1'bz;
+    assign out = io;
 endmodule
 
-module inout_basic(input oe, input in, output out);
-    wire internal;
-    assign internal = oe ? 1'bz : in;
-    inout_reg c(oe, internal);
-    assign out = internal;
+module inout_basic(input line_sel, input in1, input in2, output out);
+    tri internal;
+    tri wip;
+    wire not_sel;
+    assign not_sel = !line_sel;
+    // Select in1 if oe
+    selector s1( line_sel, in1, wip, internal, internal );
+    // Selects in2 if !oe
+    selector s2( not_sel, in2, wip, internal, internal );
+    assign out = wip;
 endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_input

@@ -0,0 +1,9 @@
+GLOBAL_SIM_BASE_CLK line_sel in1 in2
+0 1 0 0
+0 1 0 1
+0 1 1 0
+0 1 1 1
+0 0 0 0
+0 0 0 1
+0 0 1 0
+0 0 1 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_basic_output

@@ -0,0 +1,9 @@
+out
+0
+0
+1
+1
+0
+1
+0
+1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_manual_impl.v

@@ -0,0 +1,17 @@
+module selector_manual(input sel, input in, output out, input io_in, output io_out);
+    // Select if selector is set
+    assign io_out = (sel) ? in : 1'b1;
+    assign out = io_in;
+endmodule
+
+module inout_manual(input line_sel, input in1, input in2, output out);
+    tri internal;
+    tri wip;
+    wire not_sel;
+    assign not_sel = !line_sel;
+    // Select in1 if oe
+    selector_manual s1( line_sel, in1, wip, internal, internal );
+    // Selects in2 if !oe
+    selector_manual s2( not_sel, in2, wip, internal, internal );
+    assign out = wip;
+endmodule

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_manual_impl_input

@@ -0,0 +1,9 @@
+GLOBAL_SIM_BASE_CLK line_sel in1 in2
+0 1 0 0
+0 1 0 1
+0 1 1 0
+0 1 1 1
+0 0 0 0
+0 0 0 1
+0 0 1 0
+0 0 1 1

ODIN_II/regression_test/benchmark/verilog/syntax/inout-syntax/inout_manual_impl_output

@@ -0,0 +1,9 @@
+out
+0
+0
+1
+1
+0
+1
+0
+1