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AlexandreSingerAlexandreSinger
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Fixed String Constexpr
1 parent 06da883 commit b985f0f

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6 files changed

+14
-14
lines changed

6 files changed

+14
-14
lines changed

‎libs/libarchfpga/src/logic_types.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -85,10 +85,10 @@ class LogicalModels {
8585
static constexpr size_t NUM_MODELS_IN_LIBRARY = 4;
8686

8787
// Built-in library model names.
88-
static constexpr std::string MODEL_NAMES = ".names";
89-
static constexpr std::string MODEL_LATCH = ".latch";
90-
static constexpr std::string MODEL_INPUT = ".input";
91-
static constexpr std::string MODEL_OUTPUT = ".output";
88+
static constexpr const char* MODEL_NAMES = ".names";
89+
static constexpr const char* MODEL_LATCH = ".latch";
90+
static constexpr const char* MODEL_INPUT = ".input";
91+
static constexpr const char* MODEL_OUTPUT = ".output";
9292

9393
// Iterator for the logical model IDs array.
9494
typedef typename vtr::vector_map<LogicalModelId, LogicalModelId>::const_iterator model_iterator;

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1289,7 +1289,7 @@ struct ArchReader {
12891289
lut->num_pb = 1;
12901290
lut->parent_mode = mode;
12911291

1292-
lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES.c_str());
1292+
lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES);
12931293
lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES);
12941294

12951295
lut->num_ports = 2;
@@ -1396,7 +1396,7 @@ struct ArchReader {
13961396
num_ports = 1;
13971397
opad->num_ports = num_ports;
13981398
opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
1399-
opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT.c_str());
1399+
opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT);
14001400
opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT);
14011401

14021402
opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", LogicalModels::MODEL_OUTPUT);
@@ -1418,7 +1418,7 @@ struct ArchReader {
14181418
num_ports = 1;
14191419
ipad->num_ports = num_ports;
14201420
ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
1421-
ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT.c_str());
1421+
ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT);
14221422
ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT);
14231423

14241424
ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", LogicalModels::MODEL_INPUT);

‎vpr/src/base/read_netlist.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1092,7 +1092,7 @@ static size_t mark_constant_generators_rec(const t_pb* pb, const t_pb_routes& pb
10921092
}
10931093
}
10941094
}
1095-
} else if (strcmp(pb->pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT.c_str()) != 0) {
1095+
} else if (strcmp(pb->pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) != 0) {
10961096
const_gen = true;
10971097
for (i = 0; i < pb->pb_graph_node->num_input_ports && const_gen == true; i++) {
10981098
for (j = 0; j < pb->pb_graph_node->num_input_pins[i] && const_gen == true; j++) {

‎vpr/src/pack/pb_type_graph.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -294,7 +294,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node,
294294
pb_graph_node->input_pins[i_input][j].parent_node = pb_graph_node;
295295
pb_graph_node->input_pins[i_input][j].pin_count_in_cluster = pin_count_in_cluster;
296296
if (pb_graph_node->pb_type->blif_model != nullptr) {
297-
if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_OUTPUT.c_str()) == 0) {
297+
if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_OUTPUT) == 0) {
298298
pb_graph_node->input_pins[i_input][j].type = PB_PIN_OUTPAD;
299299
} else if (pb_graph_node->num_clock_ports != 0) {
300300
pb_graph_node->input_pins[i_input][j].type = PB_PIN_SEQUENTIAL;
@@ -314,7 +314,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node,
314314
pb_graph_node->output_pins[i_output][j].parent_node = pb_graph_node;
315315
pb_graph_node->output_pins[i_output][j].pin_count_in_cluster = pin_count_in_cluster;
316316
if (pb_graph_node->pb_type->blif_model != nullptr) {
317-
if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT.c_str()) == 0) {
317+
if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) == 0) {
318318
pb_graph_node->output_pins[i_output][j].type = PB_PIN_INPAD;
319319
} else if (pb_graph_node->num_clock_ports != 0) {
320320
pb_graph_node->output_pins[i_output][j].type = PB_PIN_SEQUENTIAL;

‎vpr/src/power/power.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra
133133
auto& device_ctx = g_vpr_ctx.device();
134134
auto& power_ctx = g_vpr_ctx.power();
135135

136-
if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_NAMES.c_str()) == 0) {
136+
if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) {
137137
/* LUT */
138138

139139
std::string SRAM_values;
@@ -174,7 +174,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra
174174
power_add_usage(power_usage, &sub_power_usage);
175175
delete[] input_probabilities;
176176
delete[] input_densities;
177-
} else if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_LATCH.c_str()) == 0) {
177+
} else if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) {
178178
/* Flip-Flop */
179179

180180
t_pb_graph_pin* D_pin = &pb_graph_node->input_pins[0][0];

‎vpr/src/power/power_sizing.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -405,11 +405,11 @@ static double power_count_transistors_primitive(t_pb_type* pb_type) {
405405

406406
auto& power_ctx = g_vpr_ctx.power();
407407

408-
if (strcmp(pb_type->blif_model, LogicalModels::MODEL_NAMES.c_str()) == 0) {
408+
if (strcmp(pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) {
409409
/* LUT */
410410
transistor_cnt = power_count_transistors_LUT(pb_type->num_input_pins,
411411
power_ctx.arch->LUT_transistor_size);
412-
} else if (strcmp(pb_type->blif_model, LogicalModels::MODEL_LATCH.c_str()) == 0) {
412+
} else if (strcmp(pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) {
413413
/* Latch */
414414
transistor_cnt = power_count_transistors_FF(power_ctx.arch->FF_size);
415415
} else {

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