Fixed String Constexpr

Author: AlexandreSinger

libs/libarchfpga/src/logic_types.h

@@ -85,10 +85,10 @@ class LogicalModels {
     static constexpr size_t NUM_MODELS_IN_LIBRARY = 4;
 
     // Built-in library model names.
-    static constexpr std::string MODEL_NAMES = ".names";
-    static constexpr std::string MODEL_LATCH = ".latch";
-    static constexpr std::string MODEL_INPUT = ".input";
-    static constexpr std::string MODEL_OUTPUT = ".output";
+    static constexpr const char* MODEL_NAMES = ".names";
+    static constexpr const char* MODEL_LATCH = ".latch";
+    static constexpr const char* MODEL_INPUT = ".input";
+    static constexpr const char* MODEL_OUTPUT = ".output";
 
     // Iterator for the logical model IDs array.
     typedef typename vtr::vector_map<LogicalModelId, LogicalModelId>::const_iterator model_iterator;

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -1289,7 +1289,7 @@ struct ArchReader {
         lut->num_pb = 1;
         lut->parent_mode = mode;
 
-        lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES.c_str());
+        lut->blif_model = vtr::strdup(LogicalModels::MODEL_NAMES);
         lut->model_id = get_model(arch_, LogicalModels::MODEL_NAMES);
 
         lut->num_ports = 2;
@@ -1396,7 +1396,7 @@ struct ArchReader {
         num_ports = 1;
         opad->num_ports = num_ports;
         opad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
-        opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT.c_str());
+        opad->blif_model = vtr::strdup(LogicalModels::MODEL_OUTPUT);
         opad->model_id = get_model(arch_, LogicalModels::MODEL_OUTPUT);
 
         opad->ports[0] = get_generic_port(arch_, opad, IN_PORT, "outpad", LogicalModels::MODEL_OUTPUT);
@@ -1418,7 +1418,7 @@ struct ArchReader {
         num_ports = 1;
         ipad->num_ports = num_ports;
         ipad->ports = (t_port*)vtr::calloc(num_ports, sizeof(t_port));
-        ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT.c_str());
+        ipad->blif_model = vtr::strdup(LogicalModels::MODEL_INPUT);
         ipad->model_id = get_model(arch_, LogicalModels::MODEL_INPUT);
 
         ipad->ports[0] = get_generic_port(arch_, ipad, OUT_PORT, "inpad", LogicalModels::MODEL_INPUT);

vpr/src/base/read_netlist.cpp

@@ -1092,7 +1092,7 @@ static size_t mark_constant_generators_rec(const t_pb* pb, const t_pb_routes& pb
                 }
             }
         }
-    } else if (strcmp(pb->pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT.c_str()) != 0) {
+    } else if (strcmp(pb->pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) != 0) {
         const_gen = true;
         for (i = 0; i < pb->pb_graph_node->num_input_ports && const_gen == true; i++) {
             for (j = 0; j < pb->pb_graph_node->num_input_pins[i] && const_gen == true; j++) {

vpr/src/pack/pb_type_graph.cpp

@@ -294,7 +294,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node,
                 pb_graph_node->input_pins[i_input][j].parent_node = pb_graph_node;
                 pb_graph_node->input_pins[i_input][j].pin_count_in_cluster = pin_count_in_cluster;
                 if (pb_graph_node->pb_type->blif_model != nullptr) {
-                    if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_OUTPUT.c_str()) == 0) {
+                    if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_OUTPUT) == 0) {
                         pb_graph_node->input_pins[i_input][j].type = PB_PIN_OUTPAD;
                     } else if (pb_graph_node->num_clock_ports != 0) {
                         pb_graph_node->input_pins[i_input][j].type = PB_PIN_SEQUENTIAL;
@@ -314,7 +314,7 @@ static void alloc_and_load_pb_graph(t_pb_graph_node* pb_graph_node,
                 pb_graph_node->output_pins[i_output][j].parent_node = pb_graph_node;
                 pb_graph_node->output_pins[i_output][j].pin_count_in_cluster = pin_count_in_cluster;
                 if (pb_graph_node->pb_type->blif_model != nullptr) {
-                    if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT.c_str()) == 0) {
+                    if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_INPUT) == 0) {
                         pb_graph_node->output_pins[i_output][j].type = PB_PIN_INPAD;
                     } else if (pb_graph_node->num_clock_ports != 0) {
                         pb_graph_node->output_pins[i_output][j].type = PB_PIN_SEQUENTIAL;

vpr/src/power/power.cpp

@@ -133,7 +133,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra
     auto& device_ctx = g_vpr_ctx.device();
     auto& power_ctx = g_vpr_ctx.power();
 
-    if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_NAMES.c_str()) == 0) {
+    if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) {
         /* LUT */
 
         std::string SRAM_values;
@@ -174,7 +174,7 @@ static void power_usage_primitive(t_power_usage* power_usage, t_pb* pb, t_pb_gra
         power_add_usage(power_usage, &sub_power_usage);
         delete[] input_probabilities;
         delete[] input_densities;
-    } else if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_LATCH.c_str()) == 0) {
+    } else if (strcmp(pb_graph_node->pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) {
         /* Flip-Flop */
 
         t_pb_graph_pin* D_pin = &pb_graph_node->input_pins[0][0];

vpr/src/power/power_sizing.cpp

@@ -405,11 +405,11 @@ static double power_count_transistors_primitive(t_pb_type* pb_type) {
 
     auto& power_ctx = g_vpr_ctx.power();
 
-    if (strcmp(pb_type->blif_model, LogicalModels::MODEL_NAMES.c_str()) == 0) {
+    if (strcmp(pb_type->blif_model, LogicalModels::MODEL_NAMES) == 0) {
         /* LUT */
         transistor_cnt = power_count_transistors_LUT(pb_type->num_input_pins,
                                                      power_ctx.arch->LUT_transistor_size);
-    } else if (strcmp(pb_type->blif_model, LogicalModels::MODEL_LATCH.c_str()) == 0) {
+    } else if (strcmp(pb_type->blif_model, LogicalModels::MODEL_LATCH) == 0) {
         /* Latch */
         transistor_cnt = power_count_transistors_FF(power_ctx.arch->FF_size);
     } else {