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djns1
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Updated golden results
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‎ODIN_II/SRC/output_blif.cpp

Lines changed: 27 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ static bool warn_undriven(nnode_t* node, nnet_t* net) {
6767

6868
static void merge_with_inputs(nnode_t* node, long pin_idx) {
6969
oassert(pin_idx < node->num_input_pins);
70+
oassert(node->type == OUTPUT_NODE);
7071
nnet_t* net = node->input_pins[pin_idx]->net;
7172
warn_undriven(node, net);
7273
// Merge node with all inputs with fanout of 1
@@ -134,21 +135,27 @@ static void print_output_pin(FILE* out, nnode_t* node) {
134135
fprintf(out, " %s", node->name);
135136
}
136137

138+
static char* buffer_multi_drivers(FILE* out, nnode_t* node, long pin_idx)
139+
{
140+
nnet_t* net = node->input_pins[pin_idx]->net;
141+
if (net->num_driver_pins > 1) {
142+
char* name = op_node_name(BUF_NODE, node->name);
143+
// Assign each driver to the implicit buffer
144+
for (int j = 0; j < net->num_driver_pins; j++) {
145+
fprintf(out, ".names");
146+
print_net_driver(out, node, net, j);
147+
fprintf(out, " %s\n1 1\n\n", name);
148+
}
149+
return name;
150+
}
151+
return NULL;
152+
}
153+
137154
static void print_dot_names_header(FILE* out, nnode_t* node) {
138155
char** names = (char**)vtr::calloc(node->num_input_pins, sizeof(char*));
139156

140-
// Create an implicit buffer if there are multiple drivers to the component
141157
for (int i = 0; i < node->num_input_pins; i++) {
142-
nnet_t* input_net = node->input_pins[i]->net;
143-
if (input_net->num_driver_pins > 1) {
144-
names[i] = op_node_name(BUF_NODE, node->name);
145-
// Assign each driver to the implicit buffer
146-
for (int j = 0; j < input_net->num_driver_pins; j++) {
147-
fprintf(out, ".names");
148-
print_net_driver(out, node, input_net, j);
149-
fprintf(out, " %s\n1 1\n\n", names[i]);
150-
}
151-
}
158+
names[i] = buffer_multi_drivers(out, node, i);
152159
}
153160

154161
// Print the actual header
@@ -539,21 +546,26 @@ void define_ff(nnode_t* node, FILE* out) {
539546
// grab the edge sensitivity of the flip flop
540547
const char* edge_type_str = edge_type_blif_str(node);
541548

542-
std::string input;
543-
std::string output;
544-
std::string clock_driver;
549+
char* input_driver = buffer_multi_drivers(out, node, 0);
545550

546551
fprintf(out, ".latch");
547552

548553
/* input */
549-
print_input_single_driver(out, node, 0);
554+
if(!input_driver)
555+
print_input_single_driver(out, node, 0);
556+
else {
557+
// Use the implicit buffer we created before
558+
fprintf(out, " %s", input_driver);
559+
vtr::free(input_driver);
560+
}
550561

551562
/* output */
552563
print_output_pin(out, node);
553564

554565
/* sensitivity */
555566
fprintf(out, " %s", edge_type_str);
556567

568+
// TODO Should clocks support mutliple drivers?
557569
/* clock */
558570
print_input_single_driver(out, node, 1);
559571

‎vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
2-
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.08 0.14 116128 4 0.19 -1 -1 33812 -1 -1 72 99 1 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/ch_intrinsics.v/common 76844 99 130 378 508 1 260 302 13 13 169 clb auto 0.06 638 0.59 0.00 34 1605 10 3.33e+06 2.28e+06 450788. 2667.39 0.68
3-
k4_N10_memSize16384_memData64.xml diffeq1.v common 8.00 0.10 102712 23 0.23 -1 -1 34256 -1 -1 72 162 0 5 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/diffeq1.v/common 80952 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.21 4324 1.76 0.01 50 10008 26 3.33e+06 2.61e+06 641417. 3795.37 3.79
4-
k4_N10_memSize16384_memData64.xml single_wire.v common 0.54 0.06 82948 1 0.00 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/single_wire.v/common 67096 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 6 4 1 30000 0 1761.23 195.692 0.01
5-
k4_N10_memSize16384_memData64.xml single_ff.v common 0.57 0.06 83024 1 0.00 -1 -1 29516 -1 -1 1 2 0 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/single_ff.v/common 67756 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 18 4 1 30000 30000 3112.78 345.864 0.01
1+
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
2+
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 11.75 0.03 8932 4 0.21 -1 -1 40008 -1 -1 72 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/ch_intrinsics.v/common 26652 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 638 0.28 0.00 38 1530 9 3.33e+06 2.28e+06 504671. 2986.22 0.35
3+
k4_N10_memSize16384_memData64.xml diffeq1.v common 14.27 0.02 8644 23 0.28 -1 -1 38212 -1 -1 72 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/diffeq1.v/common 31148 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.16 4324 0.62 0.00 50 10008 26 3.33e+06 2.61e+06 641417. 3795.37 2.02
4+
k4_N10_memSize16384_memData64.xml single_wire.v common 10.67 0.01 5380 1 0.01 -1 -1 33052 -1 -1 0 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/single_wire.v/common 21184 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
5+
k4_N10_memSize16384_memData64.xml single_ff.v common 10.66 0.01 5344 1 0.00 -1 -1 33384 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/single_ff.v/common 21308 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 16 9 1 30000 30000 2550.78 283.420 0.00

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